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Searched refs:CONF_GCLK_SERCOM2_CORE_SRC (Results 1 – 6 of 6) sorted by relevance

/bsp/microchip/samd51-seeed-wio-terminal/bsp/config/
A Dperipheral_clk_config.h43 #ifndef CONF_GCLK_SERCOM2_CORE_SRC
44 #define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val macro
/bsp/microchip/saml10/bsp/config/
A Dperipheral_clk_config.h107 #ifndef CONF_GCLK_SERCOM2_CORE_SRC
108 #define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val macro
/bsp/microchip/same54/bsp/config/
A Dperipheral_clk_config.h83 #ifndef CONF_GCLK_SERCOM2_CORE_SRC
84 #define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val macro
/bsp/microchip/samd51-seeed-wio-terminal/bsp/
A Ddriver_init.c29 …hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCH… in TARGET_IO_CLOCK_init()
/bsp/microchip/saml10/bsp/
A Ddriver_init.c95 …hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCH… in TARGET_IO_CLOCK_init()
/bsp/microchip/same54/bsp/
A Ddriver_init.c72 …hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCH… in TARGET_IO_CLOCK_init()

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