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Searched refs:CONF_GCLK_SERCOM3_CORE_SRC (Results 1 – 2 of 2) sorted by relevance

/bsp/microchip/samd51-adafruit-metro-m4/bsp/config/
A Dperipheral_clk_config.h43 #ifndef CONF_GCLK_SERCOM3_CORE_SRC
44 #define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val macro
/bsp/microchip/samd51-adafruit-metro-m4/bsp/
A Ddriver_init.c29 …hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCH… in TARGET_IO_CLOCK_init()

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