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Searched refs:CONTROL (Results 1 – 25 of 112) sorted by relevance

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/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/
A Daon_sleep_timer.c87 regval = AON_SLEEP_TIMER0->CONTROL.reg; in aon_sleep_timer_disable()
90 AON_SLEEP_TIMER0->CONTROL.reg = regval; in aon_sleep_timer_disable()
92 while (AON_SLEEP_TIMER0->CONTROL.reg & (1 << 14)) { in aon_sleep_timer_disable()
113 return AON_SLEEP_TIMER0->CONTROL.bit.SLEEP_TIMER_ACTIVE; in aon_sleep_timer_sleep_timer_active()
124 AON_SLEEP_TIMER0->CONTROL.reg |= AON_SLEEP_TIMER_CONTROL_IRQ_CLEAR; in aon_sleep_timer_clear_interrup()
188 aon_st_ctrl = AON_SLEEP_TIMER0->CONTROL.reg; in aon_sleep_timer_init()
190 AON_SLEEP_TIMER0->CONTROL.reg = 0; in aon_sleep_timer_init()
194 aon_st_ctrl = AON_SLEEP_TIMER0->CONTROL.reg; in aon_sleep_timer_init()
196 aon_st_ctrl = AON_SLEEP_TIMER0->CONTROL.reg; in aon_sleep_timer_init()
202 AON_SLEEP_TIMER0->CONTROL.reg = AON_SLEEP_TIMER_CONTROL_RELOAD_ENABLE; in aon_sleep_timer_init()
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_lin_drv.c112 ptr->CONTROL = 0U; in lin_master_transfer()
124 ptr->CONTROL |= LIN_CONTROL_START_REQ_MASK; in lin_master_transfer()
154 ptr->CONTROL = LIN_CONTROL_TRANSMIT_MASK; in lin_master_sent()
162 ptr->CONTROL |= LIN_CONTROL_START_REQ_MASK; in lin_master_sent()
207 ptr->CONTROL = 0U; in lin_master_receive()
209 ptr->CONTROL |= LIN_CONTROL_START_REQ_MASK; in lin_master_receive()
254 ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; in lin_slave_transfer()
276 ptr->CONTROL = LIN_CONTROL_TRANSMIT_MASK; in lin_slave_sent()
291 ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; in lin_slave_sent()
326 ptr->CONTROL = 0U; in lin_slave_receive()
[all …]
A Dhpm_mtg_drv.c45 base->TRA[tra_index].CONTROL |= MTG_TRA_CONTROL_SW_LOCK_SET(1); in mtg_get_tra_lock_result()
46 base->TRA[tra_index].CONTROL &= ~MTG_TRA_CONTROL_SW_LOCK_MASK; in mtg_get_tra_lock_result()
89 base->EVENT[event_index].CONTROL = tmp; in mtg_setup_event()
98 base->TRA[tra_index].CONTROL |= MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_SET(1); in mtg_setup_tra_limit()
102 base->TRA[tra_index].CONTROL &= ~MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_MASK; in mtg_setup_tra_limit()
105 base->TRA[tra_index].CONTROL |= MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_SET(1); in mtg_setup_tra_limit()
109 base->TRA[tra_index].CONTROL &= ~MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_MASK; in mtg_setup_tra_limit()
143 base->TRA[tra_index].CONTROL |= MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SET(1) | in mtg_setup_tra_vel_one_way()
148 base->TRA[tra_index].CONTROL |= MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SET(1); in mtg_setup_tra_vel_one_way()
152 base->TRA[tra_index].CONTROL &= ~MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_MASK; in mtg_setup_tra_vel_one_way()
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_lin_drv.h98 ptr->CONTROL |= LIN_CONTROL_RESET_INT_MASK; in lin_reset_interrupt()
108 ptr->CONTROL |= LIN_CONTROL_RESET_ERROR_MASK; in lin_reset_error()
118 ptr->CONTROL |= LIN_CONTROL_WAKEUP_REQ_MASK; in lin_wakeup()
128 ptr->CONTROL |= LIN_CONTROL_SLEEP_MASK; in lin_sleep()
138 ptr->CONTROL |= LIN_CONTROL_STOP_MASK; in lin_slave_stop()
148 ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; in lin_slave_ack()
A Dhpm_pmon_drv.h26 ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL in pmon_enable()
35 ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL in pmon_select_glitch_mode()
A Dhpm_tamp_drv.h108 ptr->TAMP[ch].CONTROL |= TAMP_TAMP_CONTROL_ENABLE_MASK; in tamp_set_ch_enable()
110 ptr->TAMP[ch].CONTROL &= ~TAMP_TAMP_CONTROL_ENABLE_MASK; in tamp_set_ch_enable()
126 ptr->TAMP[ch].CONTROL |= TAMP_TAMP_CONTROL_LOCK_MASK; in tamp_set_ch_config_lock()
128 ptr->TAMP[ch].CONTROL &= ~TAMP_TAMP_CONTROL_LOCK_MASK; in tamp_set_ch_config_lock()
A Dhpm_mtg_drv.h322 return base->TRA[tra_index].CONTROL; in mtg_get_tra_control_status()
335 return base->TRA[tra_index].CMD[cmd_index].CONTROL; in mtg_get_tra_cmd_control_status()
346 base->TRA[tra_index].CONTROL |= MTG_TRA_CONTROL_SW_LOCK_SET(1); in mtg_trig_tra_lock()
357 base->TRA[tra_index].CONTROL &= ~MTG_TRA_CONTROL_SW_LOCK_MASK; in mtg_clear_tra_lock()
680 return ((MTG_EVENT_CONTROL_EVENT_IRQ_GET(ptr->EVENT[idx].CONTROL) != 0) ? true : false); in mtg_get_irq_status()
690 ptr->EVENT[idx].CONTROL |= MTG_EVENT_CONTROL_EVENT_IRQ_MASK; in mtg_clear_irq_status()
/bsp/ti/c28x/libraries/tms320f28379d/common/source/
A DF2837xD_Dma.c194 DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; in DMACH1ModeConfig()
211 DmaRegs.CH1.CONTROL.bit.RUN = 1; in StartDMACH1()
339 DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; in DMACH2ModeConfig()
356 DmaRegs.CH2.CONTROL.bit.RUN = 1; in StartDMACH2()
483 DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; in DMACH3ModeConfig()
500 DmaRegs.CH3.CONTROL.bit.RUN = 1; in StartDMACH3()
627 DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; in DMACH4ModeConfig()
644 DmaRegs.CH4.CONTROL.bit.RUN = 1; in StartDMACH4()
771 DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; in DMACH5ModeConfig()
788 DmaRegs.CH5.CONTROL.bit.RUN = 1; in StartDMACH5()
[all …]
/bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/inc/
A DHAL_uart.h136 #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ argument
137 (((CONTROL) == UART_HardwareFlowControl_None) || \
138 ((CONTROL) == UART_HardwareFlowControl_RTS) || \
139 ((CONTROL) == UART_HardwareFlowControl_CTS) || \
140 ((CONTROL) == UART_HardwareFlowControl_RTS_CTS))
/bsp/tkm32F499/Libraries/Hal_lib/inc/
A DHAL_uart.h136 #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ argument
137 (((CONTROL) == UART_HardwareFlowControl_None) || \
138 ((CONTROL) == UART_HardwareFlowControl_RTS) || \
139 ((CONTROL) == UART_HardwareFlowControl_CTS) || \
140 ((CONTROL) == UART_HardwareFlowControl_RTS_CTS))
/bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/inc/
A DHAL_uart.h136 #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ argument
137 (((CONTROL) == UART_HardwareFlowControl_None) || \
138 ((CONTROL) == UART_HardwareFlowControl_RTS) || \
139 ((CONTROL) == UART_HardwareFlowControl_CTS) || \
140 ((CONTROL) == UART_HardwareFlowControl_RTS_CTS))
/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/
A DHAL_uart.h136 #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ argument
137 (((CONTROL) == UART_HardwareFlowControl_None) || \
138 ((CONTROL) == UART_HardwareFlowControl_RTS) || \
139 ((CONTROL) == UART_HardwareFlowControl_CTS) || \
140 ((CONTROL) == UART_HardwareFlowControl_RTS_CTS))
/bsp/Vango/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/
A Dlib_clk.c154 tmp = PMU->CONTROL; in CLK_ClockConfig()
157 PMU->CONTROL = tmp; in CLK_ClockConfig()
192 tmp = PMU->CONTROL; in CLK_ClockConfig()
195 PMU->CONTROL = tmp; in CLK_ClockConfig()
211 tmp = PMU->CONTROL; in CLK_ClockConfig()
214 PMU->CONTROL = tmp; in CLK_ClockConfig()
606 CLK_ClkInitStruct->PLLL.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLL_SEL); in CLK_GetClockConfig()
610 CLK_ClkInitStruct->PLLH.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLH_SEL); in CLK_GetClockConfig()
/bsp/Vango/v85xx/Libraries/VangoV85xx_standard_peripheral/Source/
A Dlib_clk.c162 tmp = PMU->CONTROL; in CLK_ClockConfig()
165 PMU->CONTROL = tmp; in CLK_ClockConfig()
203 tmp = PMU->CONTROL; in CLK_ClockConfig()
206 PMU->CONTROL = tmp; in CLK_ClockConfig()
223 tmp = PMU->CONTROL; in CLK_ClockConfig()
226 PMU->CONTROL = tmp; in CLK_ClockConfig()
566 CLK_ClkInitStruct->PLLL.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLL_SEL); in CLK_GetClockConfig()
570 CLK_ClkInitStruct->PLLH.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLH_SEL); in CLK_GetClockConfig()
/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/
A Dn32l40x_lpuart.h135 #define IS_LPUART_HARDWARE_FLOW_CONTROL(CONTROL) … argument
136 …(((CONTROL) == LPUART_HFCTRL_NONE) || ((CONTROL) == LPUART_HFCTRL_RTS) || ((CONTROL) == LPUART_HFC…
137 || ((CONTROL) == LPUART_HFCTRL_RTS_CTS))
/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/
A Dn32l43x_lpuart.h135 #define IS_LPUART_HARDWARE_FLOW_CONTROL(CONTROL) … argument
136 …(((CONTROL) == LPUART_HFCTRL_NONE) || ((CONTROL) == LPUART_HFCTRL_RTS) || ((CONTROL) == LPUART_HFC…
137 || ((CONTROL) == LPUART_HFCTRL_RTS_CTS))
A Dn32l43x_usart.h180 #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) … argument
181 …(((CONTROL) == USART_HFCTRL_NONE) || ((CONTROL) == USART_HFCTRL_RTS) || ((CONTROL) == USART_HFCTRL…
182 || ((CONTROL) == USART_HFCTRL_RTS_CTS))
/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/
A Dn32g43x_lpuart.h135 #define IS_LPUART_HARDWARE_FLOW_CONTROL(CONTROL) … argument
136 …(((CONTROL) == LPUART_HFCTRL_NONE) || ((CONTROL) == LPUART_HFCTRL_RTS) || ((CONTROL) == LPUART_HFC…
137 || ((CONTROL) == LPUART_HFCTRL_RTS_CTS))
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/
A Dhpm_sysctl_drv.h324 return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); in sysctl_monitor_result_is_valid()
350 …ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTR… in sysctl_monitor_set_work_mode()
363 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { in sysctl_monitor_set_limit_low()
379 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { in sysctl_monitor_set_limit_high()
399 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { in sysctl_monitor_set_limit()
711 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; in sysctl_reset_check_target_domain_wakeup_flag()
722 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; in sysctl_reset_clear_target_domain_wakeup_flag()
734 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; in sysctl_reset_check_target_domain_flag()
745 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; in sysctl_reset_clear_target_domain_flag()
756 …ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; in sysctl_reset_clear_target_domain_all_flags()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/
A Dhpm_sysctl_drv.h456 return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); in sysctl_monitor_result_is_valid()
482 …ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTR… in sysctl_monitor_set_work_mode()
495 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { in sysctl_monitor_set_limit_low()
511 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { in sysctl_monitor_set_limit_high()
529 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { in sysctl_monitor_set_limit()
842 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; in sysctl_reset_check_target_domain_wakeup_flag()
853 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; in sysctl_reset_clear_target_domain_wakeup_flag()
865 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; in sysctl_reset_check_target_domain_flag()
876 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; in sysctl_reset_clear_target_domain_flag()
887 …ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; in sysctl_reset_clear_target_domain_all_flags()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/
A Dhpm_sysctl_drv.h392 return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); in sysctl_monitor_result_is_valid()
418 …ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTR… in sysctl_monitor_set_work_mode()
431 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { in sysctl_monitor_set_limit_low()
447 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { in sysctl_monitor_set_limit_high()
467 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { in sysctl_monitor_set_limit()
779 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; in sysctl_reset_check_target_domain_wakeup_flag()
790 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; in sysctl_reset_clear_target_domain_wakeup_flag()
802 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; in sysctl_reset_check_target_domain_flag()
813 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; in sysctl_reset_clear_target_domain_flag()
824 …ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; in sysctl_reset_clear_target_domain_all_flags()
/bsp/yichip/yc3121-pos/Libraries/sdk/
A Dyc_uart.h58 #define IS_FlowCtrl(CONTROL) (((CONTROL) == FlowCtrl_None) || \ argument
59 ((CONTROL) == FlowCtrl_Enable))
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/
A Dhpm_sysctl_drv.h554 return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); in sysctl_monitor_result_is_valid()
580 …ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTR… in sysctl_monitor_set_work_mode()
593 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { in sysctl_monitor_set_limit_low()
609 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { in sysctl_monitor_set_limit_high()
629 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { in sysctl_monitor_set_limit()
907 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; in sysctl_reset_check_target_domain_wakeup_flag()
918 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; in sysctl_reset_clear_target_domain_wakeup_flag()
930 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; in sysctl_reset_check_target_domain_flag()
941 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; in sysctl_reset_clear_target_domain_flag()
952 …ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; in sysctl_reset_clear_target_domain_all_flags()
/bsp/airm2m/air32f103/libraries/AIR32F10xLib/inc/
A Dair32f10x_usart.h160 #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ argument
161 (((CONTROL) == USART_HardwareFlowControl_None) || \
162 ((CONTROL) == USART_HardwareFlowControl_RTS) || \
163 ((CONTROL) == USART_HardwareFlowControl_CTS) || \
164 ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/
A Dn32wb452_usart.h181 #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) … argument
182 …(((CONTROL) == USART_HFCTRL_NONE) || ((CONTROL) == USART_HFCTRL_RTS) || ((CONTROL) == USART_HFCTRL…
183 || ((CONTROL) == USART_HFCTRL_RTS_CTS))

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