| /bsp/at91/at91sam9g45/ |
| A D | rtconfig.py | 27 CORE = 'arm926ej-s' variable
75 DEVICE = ' --cpu=' + CORE
100 DEVICE = CORE
|
| /bsp/asm9260t/ |
| A D | rtconfig.py | 28 CORE = 'arm926ej-s' variable
76 DEVICE = ' --cpu=' + CORE
101 DEVICE = CORE
|
| /bsp/nuvoton/nk-n9h30/ |
| A D | rtconfig.py | 29 CORE = 'arm926ej-s' variable
79 DEVICE = ' --cpu=' + CORE
|
| /bsp/nuvoton/nk-980iot/ |
| A D | rtconfig.py | 29 CORE = 'arm926ej-s' variable
79 DEVICE = ' --cpu=' + CORE
|
| /bsp/nuvoton/nk-rtu980/ |
| A D | rtconfig.py | 29 CORE = 'arm926ej-s' variable
79 DEVICE = ' --cpu=' + CORE
|
| /bsp/core-v-mcu/core-v-cv32e40p/ |
| A D | readme.md | 9 
163 文件路径`OpenHW/CORE-V-SDKv0.0.0.4/registers/csr`,具体路径根据用户安装的SDK路径配置。
169 文件路径`/home/wangshun/OpenHW/CORE-V-SDKv0.0.0.4/registers/peripheral`,具体路径根据用户安装的SDK路径配置。
|
| A D | rtconfig.py | 26 CORE = 'risc-v' variable
|
| /bsp/wch/risc-v/ch569w-evt/ |
| A D | rtconfig.py | 24 CORE = 'risc-v' variable
|
| /bsp/wch/risc-v/ch32v103r-evt/ |
| A D | rtconfig.py | 24 CORE = 'risc-v' variable
|
| /bsp/hifive1/ |
| A D | rtconfig.py | 24 CORE = 'risc-v' variable
|
| /bsp/at91/at91sam9260/ |
| A D | rtconfig.py | 27 CORE = 'arm926ej-s' variable
|
| /bsp/sparkfun-redv/ |
| A D | rtconfig.py | 26 CORE = 'risc-v' variable
|
| /bsp/mm32l07x/Libraries/ |
| A D | SConscript | 5 CPPPATH = [cwd + '/CMSIS/CORE', cwd + '/MM32L0xx/Include', cwd + '/MM32L0xx/Source', cwd + '/MM32L…
|
| /bsp/phytium/board/ |
| A D | phytium_cpu.h | 45 #define RT_CORE_AFF(x) (CORE##x##_AFF | 0x80000000)
|
| /bsp/gd32/risc-v/gd32vf103v-eval/ |
| A D | rtconfig.py | 28 CORE = 'risc-v' variable
|
| /bsp/wch/risc-v/ch32v208w-r0/ |
| A D | rtconfig.py | 24 CORE = 'risc-v' variable
|
| /bsp/wch/risc-v/ch32v307v-r1/ |
| A D | rtconfig.py | 24 CORE = 'risc-v' variable
|
| /bsp/wch/risc-v/yd-ch32v307vct6/ |
| A D | rtconfig.py | 24 CORE = 'risc-v' variable
|
| /bsp/gd32/risc-v/gd32vf103r-start/ |
| A D | rtconfig.py | 28 CORE = 'risc-v' variable
|
| /bsp/xuantie/xiaohui/c910/ |
| A D | rtconfig.py | 24 CORE = 'risc-v' variable
|
| /bsp/xuantie/xiaohui/r920/ |
| A D | rtconfig.py | 24 CORE = 'risc-v' variable
|
| /bsp/xuantie/xiaohui/c906/ |
| A D | rtconfig.py | 24 CORE = 'risc-v' variable
|
| /bsp/xuantie/xiaohui/c907/ |
| A D | rtconfig.py | 24 CORE = 'risc-v' variable
|
| /bsp/xuantie/xiaohui/c908/ |
| A D | rtconfig.py | 24 CORE = 'risc-v' variable
|
| /bsp/xuantie/xiaohui/r908/ |
| A D | rtconfig.py | 24 CORE = 'risc-v' variable
|