Searched refs:CPLL (Results 1 – 2 of 2) sorted by relevance
| /bsp/rockchip/common/rk_hal/lib/hal/src/cru/ |
| A D | hal_cru_rk2108.c | 51 static struct PLL_SETUP CPLL = { variable
537 s_cpllFreq = HAL_CRU_GetPllFreq(&CPLL); in HAL_CRU_ClkGetFreq()
547 freq = HAL_CRU_GetPllFreq(&CPLL); in HAL_CRU_ClkGetFreq()
636 s_cpllFreq = HAL_CRU_GetPllFreq(&CPLL); in HAL_CRU_ClkSetFreq()
646 error = HAL_CRU_SetPllFreq(&CPLL, rate); in HAL_CRU_ClkSetFreq()
647 s_cpllFreq = HAL_CRU_GetPllFreq(&CPLL); in HAL_CRU_ClkSetFreq()
|
| /bsp/rockchip/rk3500/driver/clk/ |
| A D | clk-rk3588.c | 23 CPLL, enumerator
500 [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3588_PLL_CON(104),
2484 rate = rk_pll_get_rate(&rk3588_pll_clks[CPLL], &priv->cru, CPLL); in rk_clk_get_rate()
2688 reg_base += rk3588_pll_clks[CPLL].con_offset; in rk3588_clk_init()
2825 res_rate = rk_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_set_rate()
2826 CPLL, rate); in rk3588_clk_set_rate()
2827 priv->cpll_hz = rk_pll_get_rate(&rk3588_pll_clks[CPLL], in rk3588_clk_set_rate()
2828 priv->cru, CPLL); in rk3588_clk_set_rate()
3186 ret = rk_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_cru_init()
3187 CPLL, CPLL_HZ); in rk3588_cru_init()
|
Completed in 12 milliseconds