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/bsp/renesas/rzn2l_etherkit/
A Drzn_cfg.txt23 Cortex-R52 CPU core: CPU0
346 CPU MPU: Region: Region 00: Name: ATCM
354 CPU MPU: Region: Region 01: Name: BTCM
418 CPU MPU: Region: Region 09: Name: GIC0
434 CPU MPU: Region: Region 11: Name: Not Used
442 CPU MPU: Region: Region 12: Name: Not Used
450 CPU MPU: Region: Region 13: Name: Not Used
458 CPU MPU: Region: Region 14: Name: Not Used
538 CPU MPU: Background Region: Disabled
539 CPU MPU: Instruction Cache: Enabled
[all …]
/bsp/renesas/rzn2l_rsk/
A Drzn_cfg.txt23 Cortex-R52 CPU core: CPU0
346 CPU MPU: Region: Region 00: Name: ATCM
354 CPU MPU: Region: Region 01: Name: BTCM
418 CPU MPU: Region: Region 09: Name: GIC0
434 CPU MPU: Region: Region 11: Name: Not Used
442 CPU MPU: Region: Region 12: Name: Not Used
450 CPU MPU: Region: Region 13: Name: Not Used
458 CPU MPU: Region: Region 14: Name: Not Used
538 CPU MPU: Background Region: Disabled
539 CPU MPU: Instruction Cache: Enabled
[all …]
/bsp/phytium/
A DREADME.md5 本文档为基于 RT-Thread 的 Phytium 系列 CPU 相关 BSP 说明。
18 - 飞腾芯片产品具有谱系全、性能高、生态完善、自主化程度高等特点，目前主要包括高性能服务器 CPU（飞腾腾云S系列）、高效能桌面 CPU（飞腾腾锐D系列）、高端嵌入式 CPU（飞腾腾珑E系列）和飞腾…
20 - 本 BSP 目前支持飞腾派、飞腾腾珑E系列相关 CPU， 基于 Phytium-Standalone-SDK 进行开发。
22 - 本 BSP 支持 Phytium 系列 CPU 工作在 aarch32/aarch64 两种执行状态，开发者能够根据自己的应用场景灵活选择CPU工作状态。
/bsp/Infineon/libraries/templates/XMC7200D/libs/TARGET_APP_KIT_XMC72_EVK/COMPONENT_CM0P/TOOLCHAIN_IAR/
A Dstartup_cm0plus.s123 DCD CM0P_CpuIntr2_Handler ; DeepSleep CPU User Interrupt #2
124 DCD CM0P_CpuIntr3_Handler ; DeepSleep CPU User Interrupt #3
125 DCD CM0P_CpuIntr4_Handler ; DeepSleep CPU User Interrupt #4
131 DCD CpuUserInt8_Handler ; Active CPU User Interrupt #8
132 DCD CpuUserInt9_Handler ; Active CPU User Interrupt #9
133 DCD CpuUserInt10_Handler ; Active CPU User Interrupt #10
134 DCD CpuUserInt11_Handler ; Active CPU User Interrupt #11
135 DCD CpuUserInt12_Handler ; Active CPU User Interrupt #12
136 DCD CpuUserInt13_Handler ; Active CPU User Interrupt #13
137 DCD CpuUserInt14_Handler ; Active CPU User Interrupt #14
[all …]
/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_IAR/
A Dstartup_cm0plus.s123 DCD CM0P_CpuIntr2_Handler ; DeepSleep CPU User Interrupt #2
124 DCD CM0P_CpuIntr3_Handler ; DeepSleep CPU User Interrupt #3
125 DCD CM0P_CpuIntr4_Handler ; DeepSleep CPU User Interrupt #4
131 DCD CpuUserInt8_Handler ; Active CPU User Interrupt #8
132 DCD CpuUserInt9_Handler ; Active CPU User Interrupt #9
133 DCD CpuUserInt10_Handler ; Active CPU User Interrupt #10
134 DCD CpuUserInt11_Handler ; Active CPU User Interrupt #11
135 DCD CpuUserInt12_Handler ; Active CPU User Interrupt #12
136 DCD CpuUserInt13_Handler ; Active CPU User Interrupt #13
137 DCD CpuUserInt14_Handler ; Active CPU User Interrupt #14
[all …]
/bsp/Infineon/xmc7200-kit_xmc7200_evk/libs/TARGET_APP_KIT_XMC72_EVK/COMPONENT_CM0P/TOOLCHAIN_IAR/
A Dstartup_cm0plus.s123 DCD CM0P_CpuIntr2_Handler ; DeepSleep CPU User Interrupt #2
124 DCD CM0P_CpuIntr3_Handler ; DeepSleep CPU User Interrupt #3
125 DCD CM0P_CpuIntr4_Handler ; DeepSleep CPU User Interrupt #4
131 DCD CpuUserInt8_Handler ; Active CPU User Interrupt #8
132 DCD CpuUserInt9_Handler ; Active CPU User Interrupt #9
133 DCD CpuUserInt10_Handler ; Active CPU User Interrupt #10
134 DCD CpuUserInt11_Handler ; Active CPU User Interrupt #11
135 DCD CpuUserInt12_Handler ; Active CPU User Interrupt #12
136 DCD CpuUserInt13_Handler ; Active CPU User Interrupt #13
137 DCD CpuUserInt14_Handler ; Active CPU User Interrupt #14
[all …]
/bsp/acm32/acm32f4xx-nucleo/
A Drtconfig.py5 CPU='cortex-m33' variable
48 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata…
74 DEVICE = ' --cpu ' + CPU
116 CFLAGS += ' --cpu=' + CPU
126 AFLAGS += ' --cpu ' + CPU
/bsp/acm32/acm32f0x0-nucleo/
A Drtconfig.py5 CPU='cortex-m0' variable
46 DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections'
73 DEVICE = ' --cpu ' + CPU
119 CFLAGS += ' --cpu=' + CPU
128 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/mcx/mcxn/frdm-mcxn236/
A Drtconfig.py6 CPU='cortex-m33' variable
47 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata…
83 DEVICE = ' --cpu ' + CPU + '.fp.sp'
119 CFLAGS += ' -mcpu=' + CPU
163 CFLAGS += ' --cpu=' + CPU
174 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/mcx/mcxn/frdm-mcxn947/
A Drtconfig.py6 CPU='cortex-m33' variable
47 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata…
83 DEVICE = ' --cpu ' + CPU + '.fp.sp'
119 CFLAGS += ' -mcpu=' + CPU
163 CFLAGS += ' --cpu=' + CPU
174 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/
A Drtconfig.py6 CPU='cortex-m33' variable
47 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata…
83 DEVICE = ' --cpu ' + CPU + '.fp.sp'
119 CFLAGS += ' -mcpu=' + CPU
163 CFLAGS += ' --cpu=' + CPU
174 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/mcx/mcxa/frdm-mcxa153/
A Drtconfig.py6 CPU='cortex-m33' variable
47 …DEVICE = ' -mcpu=' + CPU + '+nodsp' + ' -mthumb -mfloat-abi=soft -ffunction-sections -fdata-sectio…
83 DEVICE = ' --cpu ' + CPU + '.fp.sp'
119 CFLAGS += ' -mcpu=' + CPU
163 CFLAGS += ' --cpu=' + CPU
174 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/mcx/mcxa/frdm-mcxa156/
A Drtconfig.py6 CPU='cortex-m33' variable
47 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata…
83 DEVICE = ' --cpu ' + CPU + '.fp.sp'
119 CFLAGS += ' -mcpu=' + CPU
163 CFLAGS += ' --cpu=' + CPU
174 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/mcx/mcxa/frdm-mcxa346/
A Drtconfig.py6 CPU='cortex-m33' variable
47 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata…
83 DEVICE = ' --cpu ' + CPU + '.fp.sp'
119 CFLAGS += ' -mcpu=' + CPU
163 CFLAGS += ' --cpu=' + CPU
174 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/mcx/mcxc/frdm-mcxc444/
A Drtconfig.py6 CPU='cortex-m0' variable
47 DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections'
83 DEVICE = ' --cpu ' + CPU + '.fp.sp'
119 CFLAGS += ' -mcpu=' + CPU
163 CFLAGS += ' --cpu=' + CPU
174 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/imx/imxrt/libraries/templates/imxrt1064xxx/
A Drtconfig.py5 CPU='cortex-m7' variable
44 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-se…
78 DEVICE = ' --cpu ' + CPU + '.fp.sp'
123 CFLAGS += ' --cpu=' + CPU
134 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/
A Drtconfig.py5 CPU='cortex-m7' variable
44 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata…
77 DEVICE = ' --cpu ' + CPU + '.fp.sp'
121 CFLAGS += ' --cpu=' + CPU
132 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/
A Drtconfig.py6 CPU='cortex-m4' variable
46 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata…
80 DEVICE = ' --cpu ' + CPU + '.fp.sp'
126 CFLAGS += ' --cpu=' + CPU
137 AFLAGS += ' --cpu ' + CPU
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/
A Dhpm_sysctl_drv.c19 *(data + i) = ptr->CPU[0].GPR[i]; in sysctl_get_cpu0_gpr()
26 uint8_t i, size = ARRAY_SIZE(ptr->CPU[0].GPR); in sysctl_cpu0_get_gpr()
32 *(data + i) = ptr->CPU[0].GPR[start + i]; in sysctl_cpu0_get_gpr()
39 uint8_t i, size = ARRAY_SIZE(ptr->CPU[0].GPR); in sysctl_cpu0_set_gpr()
46 ptr->CPU[0].GPR[start + i] = *(data + i); in sysctl_cpu0_set_gpr()
106 ptr->CPU[0].GPR[0] = entry; in sysctl_set_cpu0_entry()
107 ptr->CPU[0].GPR[1] = SYSCTL_CPU_RELEASE_KEY(0); in sysctl_set_cpu0_entry()
113 ptr->CPU[0].LP = (ptr->CPU[0].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); in sysctl_set_cpu0_lp_mode()
/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/
A Drtconfig.py6 CPU='cortex-m33' variable
47 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata…
81 DEVICE = ' --cpu ' + CPU + '.fp.sp'
127 CFLAGS += ' --cpu=' + CPU
138 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/
A Drtconfig.py6 CPU='cortex-m33' variable
47 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata…
81 DEVICE = ' --cpu ' + CPU + '.fp.sp'
127 CFLAGS += ' --cpu=' + CPU
138 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/
A Drtconfig.py6 CPU='cortex-m33' variable
47 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata…
81 DEVICE = ' --cpu ' + CPU + '.fp.sp'
127 CFLAGS += ' --cpu=' + CPU
138 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/
A Drtconfig.py6 CPU='cortex-m33' variable
47 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata…
81 DEVICE = ' --cpu ' + CPU + '.fp.sp'
127 CFLAGS += ' --cpu=' + CPU
138 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/imx/imxrt/imxrt1170-nxp-evk/
A Drtconfig.py6 CPU='cortex-m7' variable
48 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata…
84 DEVICE = ' --cpu ' + CPU + '.fp.sp'
128 CFLAGS += ' --cpu=' + CPU
139 AFLAGS += ' --cpu ' + CPU
/bsp/nxp/imx/imxrt/imxrt1021-nxp-evk/
A Drtconfig.py6 CPU='cortex-m7' variable
48 …DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata…
81 DEVICE = ' --cpu ' + CPU + '.fp.sp'
125 CFLAGS += ' --cpu=' + CPU
136 AFLAGS += ' --cpu ' + CPU

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