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Searched refs:CPUDIV (Results 1 – 12 of 12) sorted by relevance

/bsp/microchip/saml10/bsp/hri/
A Dhri_mclk_l10.h237 ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_CPUDIV(mask); in hri_mclk_set_CPUDIV_CPUDIV_bf()
244 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_get_CPUDIV_CPUDIV_bf()
253 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_write_CPUDIV_CPUDIV_bf()
256 ((Mclk *)hw)->CPUDIV.reg = tmp; in hri_mclk_write_CPUDIV_CPUDIV_bf()
277 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_read_CPUDIV_CPUDIV_bf()
285 ((Mclk *)hw)->CPUDIV.reg |= mask; in hri_mclk_set_CPUDIV_reg()
292 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_get_CPUDIV_reg()
300 ((Mclk *)hw)->CPUDIV.reg = data; in hri_mclk_write_CPUDIV_reg()
307 ((Mclk *)hw)->CPUDIV.reg &= ~mask; in hri_mclk_clear_CPUDIV_reg()
314 ((Mclk *)hw)->CPUDIV.reg ^= mask; in hri_mclk_toggle_CPUDIV_reg()
[all …]
/bsp/microchip/samc21/bsp/hri/
A Dhri_mclk_c21.h155 ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_CPUDIV(mask); in hri_mclk_set_CPUDIV_CPUDIV_bf()
162 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_get_CPUDIV_CPUDIV_bf()
171 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_write_CPUDIV_CPUDIV_bf()
174 ((Mclk *)hw)->CPUDIV.reg = tmp; in hri_mclk_write_CPUDIV_CPUDIV_bf()
195 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_read_CPUDIV_CPUDIV_bf()
203 ((Mclk *)hw)->CPUDIV.reg |= mask; in hri_mclk_set_CPUDIV_reg()
210 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_get_CPUDIV_reg()
218 ((Mclk *)hw)->CPUDIV.reg = data; in hri_mclk_write_CPUDIV_reg()
225 ((Mclk *)hw)->CPUDIV.reg &= ~mask; in hri_mclk_clear_CPUDIV_reg()
232 ((Mclk *)hw)->CPUDIV.reg ^= mask; in hri_mclk_toggle_CPUDIV_reg()
[all …]
/bsp/microchip/samc21/bsp/samc21/include/component/
A Dmclk.h100 uint8_t CPUDIV:8; /*!< bit: 0.. 7 CPU Clock Division Factor */ member
355 …__IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x04 (R/W 8) CPU Clock Division */ member
/bsp/microchip/saml10/bsp/include/component/
A Dmclk.h134 … uint8_t CPUDIV:8; /**< bit: 0..7 CPU Clock Division Factor */ member
404 …__IO MCLK_CPUDIV_Type CPUDIV; /**< Offset: 0x04 (R/W 8) CPU Clock Division… member
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_mclk_d51.h180 ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask); in hri_mclk_set_CPUDIV_DIV_bf()
187 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_get_CPUDIV_DIV_bf()
196 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_write_CPUDIV_DIV_bf()
199 ((Mclk *)hw)->CPUDIV.reg = tmp; in hri_mclk_write_CPUDIV_DIV_bf()
220 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_read_CPUDIV_DIV_bf()
228 ((Mclk *)hw)->CPUDIV.reg |= mask; in hri_mclk_set_CPUDIV_reg()
235 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_get_CPUDIV_reg()
243 ((Mclk *)hw)->CPUDIV.reg = data; in hri_mclk_write_CPUDIV_reg()
250 ((Mclk *)hw)->CPUDIV.reg &= ~mask; in hri_mclk_clear_CPUDIV_reg()
257 ((Mclk *)hw)->CPUDIV.reg ^= mask; in hri_mclk_toggle_CPUDIV_reg()
[all …]
/bsp/microchip/same54/bsp/hri/
A Dhri_mclk_e54.h180 ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask); in hri_mclk_set_CPUDIV_DIV_bf()
187 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_get_CPUDIV_DIV_bf()
196 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_write_CPUDIV_DIV_bf()
199 ((Mclk *)hw)->CPUDIV.reg = tmp; in hri_mclk_write_CPUDIV_DIV_bf()
220 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_read_CPUDIV_DIV_bf()
228 ((Mclk *)hw)->CPUDIV.reg |= mask; in hri_mclk_set_CPUDIV_reg()
235 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_get_CPUDIV_reg()
243 ((Mclk *)hw)->CPUDIV.reg = data; in hri_mclk_write_CPUDIV_reg()
250 ((Mclk *)hw)->CPUDIV.reg &= ~mask; in hri_mclk_clear_CPUDIV_reg()
257 ((Mclk *)hw)->CPUDIV.reg ^= mask; in hri_mclk_toggle_CPUDIV_reg()
[all …]
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_mclk_d51.h180 ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask); in hri_mclk_set_CPUDIV_DIV_bf()
187 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_get_CPUDIV_DIV_bf()
196 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_write_CPUDIV_DIV_bf()
199 ((Mclk *)hw)->CPUDIV.reg = tmp; in hri_mclk_write_CPUDIV_DIV_bf()
220 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_read_CPUDIV_DIV_bf()
228 ((Mclk *)hw)->CPUDIV.reg |= mask; in hri_mclk_set_CPUDIV_reg()
235 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_get_CPUDIV_reg()
243 ((Mclk *)hw)->CPUDIV.reg = data; in hri_mclk_write_CPUDIV_reg()
250 ((Mclk *)hw)->CPUDIV.reg &= ~mask; in hri_mclk_clear_CPUDIV_reg()
257 ((Mclk *)hw)->CPUDIV.reg ^= mask; in hri_mclk_toggle_CPUDIV_reg()
[all …]
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/
A Dpm.h100 uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */ member
/bsp/microchip/same54/bsp/include/component/
A Dmclk.h470 …__IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x05 (R/W 8) CPU Clock Division */ member
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Dmclk.h460 …__IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x05 (R/W 8) CPU Clock Division */ member
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/
A Dpm.h115 uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */ member
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Dmclk.h460 …__IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x05 (R/W 8) CPU Clock Division */ member

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