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Searched refs:CR (Results 1 – 25 of 486) sorted by relevance

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/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/
A Dft32f0xx_opa.c70 tmpreg = OPAx->CR; in OPA_Init()
80 OPAx->CR = tmpreg; in OPA_Init()
124 OPAx->CR |= OPA_OP1_ON; in OPA_Cmd()
129 OPAx->CR &= ~OPA_OP1_ON; in OPA_Cmd()
201 OPAx->CR |= OPA_OP1_ON; in OPA_Cali()
204 OPAx->CR |= OPA_OP1_TM; in OPA_Cali()
207 OPAx->CR &= ~OPA_OP1_NSEL; in OPA_Cali()
210 OPAx->CR |= OPA_OP1_PSEL; in OPA_Cali()
216 OPAx->CR |= OPA_OP1_TODIG; in OPA_Cali()
219 OPAx->CR &= ~OPA_OP1_FR; in OPA_Cali()
[all …]
A Dft32f0xx_flash.c112 FLASH->CR |= FLASH_CR_LOCK; in FLASH_Lock()
142 FLASH->CR |= FLASH_CR_PER; in FLASH_ErasePage()
144 FLASH->CR |= FLASH_CR_STRT; in FLASH_ErasePage()
150 FLASH->CR &= ~FLASH_CR_PER; in FLASH_ErasePage()
226 FLASH->CR |= FLASH_CR_PG; in FLASH_ProgramWord()
245 FLASH->CR &= ~FLASH_CR_PG; in FLASH_ProgramWord()
285 FLASH->CR |= FLASH_CR_PG; in FLASH_ProgramHalfWord()
293 FLASH->CR &= ~FLASH_CR_PG; in FLASH_ProgramHalfWord()
329 FLASH->CR |= FLASH_CR_PG; in FLASH_ProgramWord()
337 FLASH->CR &= ~FLASH_CR_PG; in FLASH_ProgramWord()
[all …]
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/
A Dht32f5xxxx_rtc.c61 HT_RTC->CR = 0x00000004; in RTC_DeInit()
64 HT_RTC->CR |= 0x00000005; in RTC_DeInit()
66 HT_RTC->CR = 0x00000F04; in RTC_DeInit()
82 HT_RTC->CR = (HT_RTC->CR & ~(1UL << 1)) | ((u32)Source << 1); in RTC_ClockSourceConfig()
120 HT_RTC->CR = (HT_RTC->CR & ~(1UL << 5)) | ((u32)Mode << 5); in RTC_LSESMConfig()
188 HT_RTC->CR = (HT_RTC->CR & RPRE_MASK) | Psc; in RTC_SetPrescaler()
213 HT_RTC->CR |= (1UL); in RTC_Cmd()
217 HT_RTC->CR &= ~(1UL); in RTC_Cmd()
342 HT_RTC->CR = (HT_RTC->CR & ~(1UL << 18)) | ((u32)WMode << 18); in RTC_OutConfig()
343 HT_RTC->CR = (HT_RTC->CR & ~(1UL << 17)) | ((u32)EventSel << 17); in RTC_OutConfig()
[all …]
A Dht32f5xxxx_lcd.c95 HT_LCD->CR = (HT_LCD->CR & ~(1ul << 24)) | Sel; in LCD_MaskTimeConfig()
110 HT_LCD->CR |= (1ul << 15); in LCD_HalfRLCmd()
135 HT_LCD->CR = (HT_LCD->CR & ~(1ul << 14)) | Sel; in LCD_StaticSwitchConfig()
155 HT_LCD->CR = (HT_LCD->CR & ~(1ul << 11)) | Sel; in LCD_MuxCOM7Config()
175 HT_LCD->CR = (HT_LCD->CR & ~(1ul << 10)) | Sel; in LCD_MuxCOM6Config()
195 HT_LCD->CR = (HT_LCD->CR & ~(1ul << 9)) | Sel; in LCD_MuxCOM5Config()
215 HT_LCD->CR = (HT_LCD->CR & ~(1ul << 8)) | Sel; in LCD_MuxCOM4Config()
235 HT_LCD->CR = (HT_LCD->CR & ~(1ul << 7)) | Sel; in LCD_WaveformConfig()
257 HT_LCD->CR = (HT_LCD->CR & ~(3ul << 5)) | Sel; in LCD_BiasConfig()
280 HT_LCD->CR = (HT_LCD->CR & ~(7ul << 2)) | Sel; in LCD_DutyConfig()
[all …]
A Dht32f5xxxx_pwrcu.c124 HT_PWRCU->CR = PWRRST_SET; in PWRCU_DeInit()
340 uBackUp[2] = HT_RTC->CR; in PWRCU_DeepSleep2Ex()
366 HT_RTC->CR &= (~1UL); in PWRCU_DeepSleep2Ex()
373 HT_RTC->CR &= (~1UL); in PWRCU_DeepSleep2Ex()
378 HT_RTC->CR = uBackUp[2]; in PWRCU_DeepSleep2Ex()
411 HT_RTC->CR &= ~(1UL << 2); in PWRCU_PowerDown()
414 HT_RTC->CR |= (1UL << 2); in PWRCU_PowerDown()
734 HT_PWRCU->CR = (HT_PWRCU->CR & VREG_V_MASK) | Volt; in PWRCU_SetVREG()
751 HT_PWRCU->CR = (HT_PWRCU->CR & VREG_M_MASK) | Mode; in PWRCU_VREGConfig()
802 HT_PWRCU->CR = (HT_PWRCU->CR & WUP0TYPE_MASK) | (Type << 16); in PWRCU_WakeupMultiPinCmd()
[all …]
/bsp/mm32l07x/Libraries/MM32L0xx/Source/
A Dsystem_MM32L0xx.c177 RCC->CR |= (uint32_t)0x1; in SystemInit()
184 RCC->CR &= (uint32_t)0xFEF6FFFF; in SystemInit()
367 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo24()
454 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo36()
540 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo48()
567 RCC->CR|=RCC_CR_HSION; in SetSysClockTo24_HSI()
575 RCC->CR &=~(0x1f<<26); in SetSysClockTo24_HSI()
596 RCC->CR|=RCC_CR_HSION; in SetSysClockTo36_HSI()
604 RCC->CR &=~(0x1f<<26); in SetSysClockTo36_HSI()
625 RCC->CR|=RCC_CR_HSION; in SetSysClockTo48_HSI()
[all …]
/bsp/mm32l3xx/Libraries/MM32L3xx/Source/
A Dsystem_MM32L3xx.c388 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo24()
476 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo36()
562 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo48()
650 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo56()
738 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo72()
854 RCC->CR|=RCC_CR_HSION; in SetSysClockTo48_HSI()
862 RCC->CR &=~(0x1f<<26); in SetSysClockTo48_HSI()
881 RCC->CR|=RCC_CR_HSION; in SetSysClockTo72_HSI()
889 RCC->CR &=~(0x1f<<26); in SetSysClockTo72_HSI()
908 RCC->CR|=RCC_CR_HSION; in SetSysClockTo96_HSI()
[all …]
/bsp/mm32f103x/Libraries/MM32F103/Source/
A Dsystem_MM32F103.c393 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo24()
484 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo36()
573 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo48()
664 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo56()
755 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo72()
875 RCC->CR |= RCC_CR_HSION; in SetSysClockTo48_HSI()
883 RCC->CR &= ~(0x1f << 26); in SetSysClockTo48_HSI()
902 RCC->CR |= RCC_CR_HSION; in SetSysClockTo72_HSI()
910 RCC->CR &= ~(0x1f << 26); in SetSysClockTo72_HSI()
929 RCC->CR |= RCC_CR_HSION; in SetSysClockTo96_HSI()
[all …]
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_ll_pwr.h203 SET_BIT(PWR->CR, PWR_CR_LPRUN); in LL_PWR_EnableLowPowerRunMode()
213 CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); in LL_PWR_DisableLowPowerRunMode()
297 SET_BIT(PWR->CR, PWR_CR_DBP); in LL_PWR_EnableBkUpAccess()
307 CLEAR_BIT(PWR->CR, PWR_CR_DBP); in LL_PWR_DisableBkUpAccess()
446 SET_BIT(PWR->CR, PWR_CR_PVDE); in LL_PWR_EnablePVD()
531 SET_BIT(PWR->CR, PWR_CR_ULP); in LL_PWR_EnableUltraLowPower()
541 CLEAR_BIT(PWR->CR, PWR_CR_ULP); in LL_PWR_DisableUltraLowPower()
562 SET_BIT(PWR->CR, PWR_CR_FWU); in LL_PWR_EnableFastWakeUp()
573 CLEAR_BIT(PWR->CR, PWR_CR_FWU); in LL_PWR_DisableFastWakeUp()
664 SET_BIT(PWR->CR, PWR_CR_CSBF); in LL_PWR_ClearFlag_SB()
[all …]
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/src/
A Dhk32f0xx_flash.c224 FLASH->CR |= FLASH_CR_LOCK; in FLASH_Lock()
251 FLASH->CR |= FLASH_CR_PER; in FLASH_ErasePage()
253 FLASH->CR |= FLASH_CR_STRT; in FLASH_ErasePage()
259 FLASH->CR &= ~FLASH_CR_PER; in FLASH_ErasePage()
285 FLASH->CR |= FLASH_CR_MER; in FLASH_EraseAllPages()
286 FLASH->CR |= FLASH_CR_STRT; in FLASH_EraseAllPages()
324 FLASH->CR |= FLASH_CR_PG; in FLASH_ProgramWord()
379 FLASH->CR |= FLASH_CR_PG; in FLASH_ProgramHalfWord()
387 FLASH->CR &= ~FLASH_CR_PG; in FLASH_ProgramHalfWord()
474 FLASH->CR &= ~FLASH_CR_OPTWRE; in FLASH_OB_Lock()
[all …]
/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/
A Dsystem_ft32f0xx.c130 RCC->CR |= (uint32_t)0x00000001; in SystemInit()
136 RCC->CR &= (uint32_t)0xFEF6FFFF; in SystemInit()
139 RCC->CR &= (uint32_t)0xFFFBFFFF; in SystemInit()
284 RCC->CR |= ((uint32_t)RCC_CR_HSEON); in SetSysClockToHSE()
341 RCC->CR |= ((uint32_t)RCC_CR_HSION); in SetSysClockTo24()
375 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo24()
444 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo36()
513 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo48()
582 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo56()
651 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo72()
[all …]
/bsp/mm32f327x/Libraries/MM32F327x/Source/
A Dsystem_mm32f327x.c569 RCC->CR |= RCC_CR_HSION; in SetSysClockToXX()
580 PWR->CR |= 3 << 14; in SetSysClockToXX()
638 RCC->CR |= RCC_CR_PLLON; in SetSysClockToXX()
668 RCC->CR |= RCC_CR_HSION; in SetSysClockTo24_HSI()
683 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo24_HSI()
702 RCC->CR |= RCC_CR_HSION; in SetSysClockTo36_HSI()
715 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo36_HSI()
734 RCC->CR |= RCC_CR_HSION; in SetSysClockTo48_HSI()
752 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo48_HSI()
773 RCC->CR |= RCC_CR_HSION; in SetSysClockToXX_HSI()
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_gptmr_drv.h143 ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR in gptmr_channel_enable()
156 ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CNTRST_MASK; in gptmr_channel_reset_count()
175 ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CNTUPT_MASK; in gptmr_channel_update_count()
189 ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR in gptmr_channel_select_synci_valid_edge()
207 ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR in gptmr_channel_enable_dma_request()
317 ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CEN_MASK; in gptmr_start_counter()
328 ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CEN_MASK; in gptmr_stop_counter()
339 ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CMPEN_MASK; in gptmr_enable_cmp_output()
362 …ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR & ~GPTMR_CHANNEL_CR_CAPMODE_MASK) | GPTMR_C… in gptmr_channel_set_capmode()
468 …ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR & ~GPTMR_CHANNEL_CR_CNT_MODE_MASK) | GPTMR_… in gptmr_channel_set_counter_mode()
[all …]
/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/
A Dald_tsense.c87 TSENSE->CR = 0; in ald_tsense_init()
89 SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); in ald_tsense_init()
90 SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); in ald_tsense_init()
128 SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); in ald_tsense_source_select()
131 SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); in ald_tsense_source_select()
173 SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); in ald_tsense_get_value()
180 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); in ald_tsense_get_value()
191 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); in ald_tsense_get_value()
199 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); in ald_tsense_get_value()
217 SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); in ald_tsense_get_value_by_it()
[all …]
/bsp/airm2m/air32f103/libraries/AIR32F10xLib/src/
A Dair32f10x_flash.c349 FLASH->CR |= CR_LOCK_Set; in FLASH_Lock()
369 FLASH->CR |= CR_LOCK_Set; in FLASH_LockBank1()
407 FLASH->CR|= CR_PER_Set; in FLASH_ErasePage()
443 FLASH->CR|= CR_PER_Set; in FLASH_ErasePage()
445 FLASH->CR|= CR_STRT_Set; in FLASH_ErasePage()
477 FLASH->CR |= CR_MER_Set; in FLASH_EraseAllPages()
504 FLASH->CR |= CR_MER_Set; in FLASH_EraseAllPages()
886 FLASH->CR |= CR_PG_Set; in FLASH_ProgramWord()
973 FLASH->CR |= CR_PG_Set; in FLASH_ProgramHalfWord()
1387 FLASH->CR |= FLASH_IT; in FLASH_ITConfig()
[all …]
A Dsystem_air32f10x.c216 RCC->CR |= (uint32_t)0x00000001; in SystemInit()
638 RCC->CR |= RCC_CR_PLL2ON; in SetSysClockTo24()
654 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo24()
742 RCC->CR |= RCC_CR_PLL2ON; in SetSysClockTo36()
755 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo36()
837 RCC->CR |= RCC_CR_PLL2ON; in SetSysClockTo48()
855 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo48()
938 RCC->CR |= RCC_CR_PLL2ON; in SetSysClockTo56()
957 RCC->CR |= RCC_CR_PLLON; in SetSysClockTo56()
1041 RCC->CR |= RCC_CR_PLL2ON; in SetSysClockTo72()
[all …]
/bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/src/
A DHAL_flash.c200 FLASH->CR |= CR_LOCK_Set; in FLASH_Lock()
222 FLASH->CR|= CR_PER_Set; in FLASH_ErasePage()
224 FLASH->CR|= CR_STRT_Set; in FLASH_ErasePage()
256 FLASH->CR |= CR_MER_Set; in FLASH_EraseAllPages()
257 FLASH->CR |= CR_STRT_Set; in FLASH_EraseAllPages()
295 FLASH->CR |= CR_OPTER_Set; in FLASH_EraseOptionBytes()
296 FLASH->CR |= CR_STRT_Set; in FLASH_EraseOptionBytes()
356 FLASH->CR |= CR_PG_Set; in FLASH_ProgramWord()
412 FLASH->CR |= CR_PG_Set; in FLASH_ProgramHalfWord()
568 FLASH->CR |= CR_STRT_Set; in FLASH_ReadOutProtection()
[all …]
A DHAL_pwr.c140 PWR->CR |= 0x00000100; in PWR_BackupAccessCmd()
144 PWR->CR &= 0xfffffeff; in PWR_BackupAccessCmd()
162 PWR->CR |= 0x00000010; in PWR_PVDCmd()
166 PWR->CR &= 0xffffffef; in PWR_PVDCmd()
193 tmpreg = PWR->CR; in PWR_PVDLevelConfig()
199 PWR->CR = tmpreg; in PWR_PVDLevelConfig()
245 tmpreg = PWR->CR; in PWR_EnterSTOPMode()
251 PWR->CR = tmpreg; in PWR_EnterSTOPMode()
276 PWR->CR |= CR_CWUF_Set; in PWR_EnterSTANDBYMode()
278 PWR->CR |= CR_PDDS_Set; in PWR_EnterSTANDBYMode()
[all …]
/bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/src/
A DHAL_flash.c200 FLASH->CR |= CR_LOCK_Set; in FLASH_Lock()
222 FLASH->CR|= CR_PER_Set; in FLASH_ErasePage()
224 FLASH->CR|= CR_STRT_Set; in FLASH_ErasePage()
257 FLASH->CR |= CR_MER_Set; in FLASH_EraseAllPages()
258 FLASH->CR |= CR_STRT_Set; in FLASH_EraseAllPages()
293 FLASH->CR |= CR_OPTER_Set; in FLASH_EraseOptionBytes()
295 FLASH->CR |= CR_STRT_Set; in FLASH_EraseOptionBytes()
356 FLASH->CR |= CR_PG_Set; in FLASH_ProgramWord()
414 FLASH->CR |= CR_PG_Set; in FLASH_ProgramHalfWord()
583 FLASH->CR |= CR_STRT_Set; in FLASH_ReadOutProtection()
[all …]
A DHAL_pwr.c139 PWR->CR |= 0x00000100; in PWR_BackupAccessCmd()
143 PWR->CR &= 0xfffffeff; in PWR_BackupAccessCmd()
161 PWR->CR |= 0x00000010; in PWR_PVDCmd()
165 PWR->CR &= 0xffffffef; in PWR_PVDCmd()
193 tmpreg = PWR->CR; in PWR_PVDLevelConfig()
199 PWR->CR = tmpreg; in PWR_PVDLevelConfig()
245 tmpreg = PWR->CR; in PWR_EnterSTOPMode()
251 PWR->CR = tmpreg; in PWR_EnterSTOPMode()
277 PWR->CR |= CR_CWUF_Set; in PWR_EnterSTANDBYMode()
279 PWR->CR |= CR_PDDS_Set; in PWR_EnterSTANDBYMode()
[all …]
/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/
A DHAL_flash.c200 FLASH->CR |= CR_LOCK_Set; in FLASH_Lock()
222 FLASH->CR |= CR_PER_Set; in FLASH_ErasePage()
224 FLASH->CR |= CR_STRT_Set; in FLASH_ErasePage()
257 FLASH->CR |= CR_MER_Set; in FLASH_EraseAllPages()
258 FLASH->CR |= CR_STRT_Set; in FLASH_EraseAllPages()
293 FLASH->CR |= CR_OPTER_Set; in FLASH_EraseOptionBytes()
295 FLASH->CR |= CR_STRT_Set; in FLASH_EraseOptionBytes()
356 FLASH->CR |= CR_PG_Set; in FLASH_ProgramWord()
414 FLASH->CR |= CR_PG_Set; in FLASH_ProgramHalfWord()
583 FLASH->CR |= CR_STRT_Set; in FLASH_ReadOutProtection()
[all …]
/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/
A Dald_tsense.c86 TSENSE->CR = 0; in ald_tsense_init()
126 SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); in ald_tsense_source_select()
129 SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); in ald_tsense_source_select()
171 SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); in ald_tsense_get_value()
178 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); in ald_tsense_get_value()
189 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); in ald_tsense_get_value()
197 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); in ald_tsense_get_value()
215 SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); in ald_tsense_get_value_by_it()
233 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); in ald_tsense_irq_handler()
240 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); in ald_tsense_irq_handler()
[all …]
/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/
A DHAL_RTC.c225 RTC->CR |= RTC_CR_ALM_EN; in HAL_RTC_AlarmEnable()
237 RTC->CR &= ~RTC_CR_ALM_EN; in HAL_RTC_AlarmDisable()
278 RTC->CR |= RTC_CR_TAMPFLTCLK; in HAL_RTC_Tamper()
282 RTC->CR |= (fp_Temper->u32_Filter - 2) << 13; in HAL_RTC_Tamper()
286 RTC->CR |= RTC_CR_TAMP1EN; in HAL_RTC_Tamper()
315 RTC->CR |= RTC_CR_TAMPFLTCLK; in HAL_RTC_Tamper()
323 RTC->CR |= RTC_CR_TAMP2EN; in HAL_RTC_Tamper()
351 RTC->CR |= RTC_CR_TAMP1EN; in HAL_RTC_TamperEnable()
355 RTC->CR |= RTC_CR_TAMP2EN; in HAL_RTC_TamperEnable()
370 RTC->CR &= ~RTC_CR_TAMP1EN; in HAL_RTC_TamperDisable()
[all …]
/bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Src/
A DHAL_RTC.c225 RTC->CR |= RTC_CR_ALM_EN; in HAL_RTC_AlarmEnable()
237 RTC->CR &= ~RTC_CR_ALM_EN; in HAL_RTC_AlarmDisable()
278 RTC->CR |= RTC_CR_TAMPFLTCLK; in HAL_RTC_Tamper()
282 RTC->CR |= (fp_Temper->u32_Filter - 2) << 13; in HAL_RTC_Tamper()
286 RTC->CR |= RTC_CR_TAMP1EN; in HAL_RTC_Tamper()
315 RTC->CR |= RTC_CR_TAMPFLTCLK; in HAL_RTC_Tamper()
323 RTC->CR |= RTC_CR_TAMP2EN; in HAL_RTC_Tamper()
351 RTC->CR |= RTC_CR_TAMP1EN; in HAL_RTC_TamperEnable()
355 RTC->CR |= RTC_CR_TAMP2EN; in HAL_RTC_TamperEnable()
370 RTC->CR &= ~RTC_CR_TAMP1EN; in HAL_RTC_TamperDisable()
[all …]
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/
A Dfm33lc0xx_fl_opa.h205 CLEAR_BIT(OPAx->CR, OPA_CR_BUFFEN_Msk); in FL_OPA_EnableVrefBuffer()
227 CLEAR_BIT(OPAx->CR, OPA_CR_BUFFEN_Msk); in FL_OPA_DisableVrefBuffer()
238 SET_BIT(OPAx->CR, OPA_CR_BUFBYP_Msk); in FL_OPA_EnableBypassVrefBuffer()
260 CLEAR_BIT(OPAx->CR, OPA_CR_BUFBYP_Msk); in FL_OPA_DisableBypassVrefBuffer()
335 SET_BIT(OPAx->CR, OPA_CR_DF_Msk); in FL_OPA_EnableCOMPModeDigitalFilter()
357 CLEAR_BIT(OPAx->CR, OPA_CR_DF_Msk); in FL_OPA_DisableCOMPModeDigitalFilter()
368 SET_BIT(OPAx->CR, OPA_CR_VN_EXC_Msk); in FL_OPA_PGA_EnableINNConnectToPin()
463 SET_BIT(OPAx->CR, OPA_CR_LPM_Msk); in FL_OPA_EnableLowPowerMode()
485 CLEAR_BIT(OPAx->CR, OPA_CR_LPM_Msk); in FL_OPA_DisableLowPowerMode()
496 SET_BIT(OPAx->CR, OPA_CR_EN_Msk); in FL_OPA_Enable()
[all …]

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