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Searched refs:CRL_APB_GEM_DIV1_MASK (Results 1 – 2 of 2) sorted by relevance

/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/
A Dxemacpsif.h82 #define CRL_APB_GEM_DIV1_MASK 0x003F0000 macro
/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/
A Dxemacpsif_physpeed.c1075 CrlApbGemCtrl &= ~CRL_APB_GEM_DIV1_MASK; in SetUpSLCRDivisors()

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