Home
last modified time | relevance | path

Searched refs:CS (Results 1 – 25 of 81) sorted by relevance

1234

/bsp/nv32f100x/lib/inc/
A Dacmp.h238 pACMPx->CS |= ACMP_CS_ACE_MASK; in ACMP_Enable()
256 pACMPx->CS &= ~ACMP_CS_ACE_MASK; in ACMP_Disable()
273 pACMPx->CS &= ~ACMP_CS_ACMOD_MASK; in ACMP_SelectIntMode()
292 pACMPx->CS |= ACMP_CS_ACOPE_MASK; in ACMP_EnablePinOut()
310 pACMPx->CS &= ~ACMP_CS_ACOPE_MASK; in ACMP_DisablePinOut()
327 pACMPx->CS &= ~ACMP_CS_HYST_MASK; in ACMP_SelectHyst()
328 pACMPx->CS |= u8HystSelect; in ACMP_SelectHyst()
346 pACMPx->CS |= ACMP_CS_ACIE_MASK; in ACMP_EnableInterrupt()
364 pACMPx->CS &= ~ACMP_CS_ACIE_MASK; in ACMP_DisableInterrupt()
382 return (pACMPx->CS & ACMP_CS_ACF_MASK); in ACMP_GetFlag()
[all …]
/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/
A Dhal_eth.c348 if (DMATxDescToSet->CS & ETH_DMA_TDES_OWN) in ETH_Prepare_Transmit_Descriptors()
368 temp_desc->CS |= ETH_DMA_TDES_OWN; in ETH_Prepare_Transmit_Descriptors()
386 temp_desc->CS |= ETH_DMA_TDES_OWN; in ETH_Prepare_Transmit_Descriptors()
410 temp_desc->CS = ETH_DMA_RDES_OWN; in ETH_DMARxDescChainInit()
482 return (FlagStatus)(ptr_desc->CS & flag); in ETH_GetDMATxDescFlagStatus()
492 ptr_desc->CS |= ETH_DMA_TDES_OWN; in ETH_SetDMATxDescOwnBit()
502 ptr_desc->CS |= val; in ETH_DMATxDescFrameSegmentConfig()
507 ptr_desc->CS |= val; in ETH_DMATxDescChecksumInsertionConfig()
532 return (FlagStatus)(ptr_desc->CS & flag); in ETH_GetDMARxDescFlagStatus()
537 ptr_desc->CS |= ETH_DMA_RDES_OWN; in ETH_SetDMARxDescOwnBit()
[all …]
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_wdog32.h195 base->CS |= WDOG_CS_EN_MASK; in WDOG32_Enable()
209 base->CS &= ~WDOG_CS_EN_MASK; in WDOG32_Disable()
226 base->CS |= mask; in WDOG32_EnableInterrupts()
243 base->CS &= ~mask; in WDOG32_DisableInterrupts()
263 return (base->CS & (WDOG_CS_EN_MASK | WDOG_CS_FLG_MASK)); in WDOG32_GetStatusFlags()
325 if ((base->CS) & WDOG_CS_CMD32EN_MASK) in WDOG32_Unlock()
346 if ((base->CS) & WDOG_CS_CMD32EN_MASK) in WDOG32_Refresh()
A Dfsl_wdog32.c19 base->CS |= WDOG_CS_FLG_MASK; in WDOG32_ClearStatusFlags()
60 base->CS = value; in WDOG32_Init()
/bsp/tkm32F499/Libraries/Hal_lib/inc/
A DHAL_spi.h249 #define IS_SPI_CS(CS) (((CS) == SPI_CS_BIT0) || ((CS) == SPI_CS_BIT1)||\ argument
250 ((CS) == SPI_CS_BIT2) || ((CS) == SPI_CS_BIT3)||\
251 ((CS) == SPI_CS_BIT4) || ((CS) == SPI_CS_BIT5)||\
252 ((CS) == SPI_CS_BIT6) || ((CS) == SPI_CS_BIT7))
/bsp/airm2m/air105/libraries/HAL_Driver/Src/
A Dcore_otp.c39 OTP->CS |= 1; in OTP_Write()
40 while((OTP->CS & 0x00000001)){;} in OTP_Write()
41 OTP->CS &= ~(0x07 << 1); in OTP_Write()
50 while(!(OTP->CS & 0x80000000)){;} in OTP_Read()
/bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/inc/
A DHAL_spi.h293 #define IS_SPI_CS(CS) (((CS) == SPI_CS_BIT0) || ((CS) == SPI_CS_BIT1)||\ argument
294 ((CS) == SPI_CS_BIT2) || ((CS) == SPI_CS_BIT3)||\
295 ((CS) == SPI_CS_BIT4) || ((CS) == SPI_CS_BIT5)||\
296 ((CS) == SPI_CS_BIT6) || ((CS) == SPI_CS_BIT7))
/bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/inc/
A DHAL_spi.h293 #define IS_SPI_CS(CS) (((CS) == SPI_CS_BIT0) || ((CS) == SPI_CS_BIT1)||\ argument
294 ((CS) == SPI_CS_BIT2) || ((CS) == SPI_CS_BIT3)||\
295 ((CS) == SPI_CS_BIT4) || ((CS) == SPI_CS_BIT5)||\
296 ((CS) == SPI_CS_BIT6) || ((CS) == SPI_CS_BIT7))
/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/
A DHAL_spi.h293 #define IS_SPI_CS(CS) (((CS) == SPI_CS_BIT0) || ((CS) == SPI_CS_BIT1)||\ argument
294 ((CS) == SPI_CS_BIT2) || ((CS) == SPI_CS_BIT3)||\
295 ((CS) == SPI_CS_BIT4) || ((CS) == SPI_CS_BIT5)||\
296 ((CS) == SPI_CS_BIT6) || ((CS) == SPI_CS_BIT7))
/bsp/nv32f100x/lib/src/
A Dacmp.c86 pACMPx->CS = pConfig->sCtrlStatus.byte; in ACMP_Init()
124 if(pACMPx->CS & ACMP_CS_ACIE_MASK) in ACMP_DeInit()
129 if(pACMPx->CS & ACMP_CS_ACIE_MASK) in ACMP_DeInit()
133 pACMPx->CS = 0; in ACMP_DeInit()
/bsp/frdm-k64f/device/MK64F12/
A Dfsl_flexbus.c98 base->CS[chip].CSMR = 0x0000U; in FLEXBUS_Init()
100 base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK); in FLEXBUS_Init()
102 base->CS[chip].CSCR = 0x0000U; in FLEXBUS_Init()
124 base->CS[chip].CSAR = reg_value; in FLEXBUS_Init()
132 base->CS[chip].CSMR = reg_value; in FLEXBUS_Init()
158 base->CS[chip].CSCR = reg_value; in FLEXBUS_Init()
A Dfsl_flexcan.c391 base->MB[i].CS = 0x0; in FLEXCAN_Reset()
607 base->MB[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); in FLEXCAN_SetTxMbConfig()
611 base->MB[mbIdx].CS = 0; in FLEXCAN_SetTxMbConfig()
630 base->MB[mbIdx].CS = 0; in FLEXCAN_SetRxMbConfig()
656 base->MB[mbIdx].CS = cs_temp; in FLEXCAN_SetRxMbConfig()
665 volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS); in FLEXCAN_SetRxFifoConfig()
807 …base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); in FLEXCAN_WriteTxMb()
831 base->MB[mbIdx].CS = cs_temp; in FLEXCAN_WriteTxMb()
834 base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); in FLEXCAN_WriteTxMb()
858 cs_temp = base->MB[mbIdx].CS; in FLEXCAN_ReadRxMb()
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_ppi_drv.c34 ppi->CS[index].CFG0 = tmp; in ppi_config_cs_pin()
44 ppi->CS[index].CFG1 = tmp; in ppi_config_cs_pin()
50 ppi->CS[index].CFG3 = tmp; in ppi_config_cs_pin()
56 ppi->CS[index].CFG4 = tmp; in ppi_config_cs_pin()
66 ppi->CS[index].CFG2 = tmp; in ppi_config_cs_pin()
/bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Src/
A DHAL_SPI.c165 hspi->Instance->CS &= (~SPI_CS_CS0); in HAL_SPI_IRQHandler()
438 hspi->Instance->CS |= SPI_CS_CS0; in HAL_SPI_Transmit()
501 hspi->Instance->CS &= (~SPI_CS_CS0); in HAL_SPI_Transmit()
549 hspi->Instance->CS |= SPI_CS_CS0; in HAL_SPI_Transmit_DMA()
630 hspi->Instance->CS |= SPI_CS_CS0; in HAL_SPI_Receive()
670 hspi->Instance->CS &= (~SPI_CS_CS0); in HAL_SPI_Receive()
715 hspi->Instance->CS |= SPI_CS_CS0; in HAL_SPI_Receive_DMA()
784 hspi->Instance->CS |= SPI_CS_CS0; in HAL_SPI_Transmit_IT()
844 hspi->Instance->CS |= SPI_CS_CS0; in HAL_SPI_Receive_IT()
922 hspi->Instance->CS |= SPI_CS_CS0; in HAL_SPI_TransmitReceive()
[all …]
/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/
A DHAL_SPI.c181 hspi->Instance->CS &= (~SPI_CS_CS0); in HAL_SPI_IRQHandler()
474 hspi->Instance->CS |= SPI_CS_CS0; in HAL_SPI_Transmit()
537 hspi->Instance->CS &= (~SPI_CS_CS0); in HAL_SPI_Transmit()
585 hspi->Instance->CS |= SPI_CS_CS0; in HAL_SPI_Transmit_DMA()
667 hspi->Instance->CS |= SPI_CS_CS0; in HAL_SPI_Receive()
707 hspi->Instance->CS &= (~SPI_CS_CS0); in HAL_SPI_Receive()
752 hspi->Instance->CS |= SPI_CS_CS0; in HAL_SPI_Receive_DMA()
821 hspi->Instance->CS |= SPI_CS_CS0; in HAL_SPI_Transmit_IT()
881 hspi->Instance->CS |= SPI_CS_CS0; in HAL_SPI_Receive_IT()
956 hspi->Instance->CS |= SPI_CS_CS0; in HAL_SPI_TransmitReceive()
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_ppi_drv.h208 …ppi->CS[index].CFG2 = (ppi->CS[index].CFG2 & ~PPI_CS_CFG2_DM_POLARITY_MASK) | PPI_CS_CFG2_DM_POLAR… in ppi_config_dm_pin_polarity()
/bsp/nrf5x/nrf5340/
A DREADME.md52 - SPI_HS: SCK(P0.08), MOSI(P0.09), MISO(P0.10), CS(P0.11) => 连接MX25 QSPI FLASH
58 - NRF7002(QSPI): CS(P0.18), CLK(P0.17), QSPI0(P0.13), QSPI1(P0.14), QSPI2(P0.15), QSPI3(P0.16)
/bsp/stm32/stm32l475-atk-pandora/applications/arduino_pinout/
A DREADME.md55 | 28 (D28, SS) | PD5 | 是 | 无线模块 片选 CS |
63 | 36 (D36) | PD7 | 是 | LCD 片选 CS |
/bsp/renesas/rzn2l_etherkit/rzn_cfg/fsp_cfg/bsp/
A Dbsp_pin_cfg.h97 #define CS (BSP_IO_PORT_21_PIN_1) macro
/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/
A Dbsp_pin_cfg.h97 #define CS (BSP_IO_PORT_21_PIN_1) macro
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/
A Dsystem_RV32M1_ri5cy.c363 WDOG0->CS = (uint32_t) ((WDOG0->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK; in SystemInit()
A Dsystem_RV32M1_zero_riscy.c366 WDOG1->CS = (uint32_t) ((WDOG1->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK; in SystemInit()
/bsp/stm32/stm32u575-st-nucleo/applications/arduino_pinout/
A DREADME.md35 | 10 (D10) | PD14 | 是 | SPI1 片选 CS |
/bsp/synwit/swm320-mini/board/
A DKconfig248 bool "Enable SPI0 BUS(CS/P22,MISO/P19,MOSI/P18,CLK/P23)"
252 bool "Enable SPI1 BUS(CS/B6,MISO/B3,MOSI/B2,CLK/B1)"
/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/
A DKconfig143 hex "CS pin index"

Completed in 59 milliseconds

1234