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Searched refs:CSR (Results 1 – 25 of 190) sorted by relevance

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/bsp/airm2m/air32f103/libraries/AIR32F10xLib/src/
A Dair32f10x_crc.c45 …CRC->CSR = (CRC->CSR | REV_OUT_SEL_SET | REV_IN_SEL_SET) & (~XOR_OUT_SEL_SET) & ~POLY_SEL_SET & ~… in CRC_CalcBlockCRC()
52 …CRC->CSR = (CRC->CSR | REV_OUT_SEL_SET | REV_IN_SEL_SET | XOR_OUT_SEL_SET) & ~POLY_SEL_SET & ~TYPE… in CRC_CalcBlockCRC()
58 …CRC->CSR = (CRC->CSR | REV_OUT_SEL_SET | REV_IN_SEL_SET | XOR_OUT_SEL_SET) & ~POLY_SEL_SET & ~TYPE… in CRC_CalcBlockCRC()
64 …CRC->CSR = (CRC->CSR | REV_OUT_SEL_SET | REV_IN_SEL_SET) & (~XOR_OUT_SEL_SET) & ~POLY_SEL_SET & ~T… in CRC_CalcBlockCRC()
70 …CRC->CSR = (((CRC->CSR | REV_OUT_SEL_SET | REV_IN_SEL_SET) & (~XOR_OUT_SEL_SET)) | POLY_SEL_SET) &… in CRC_CalcBlockCRC()
76 …CRC->CSR = ((((CRC->CSR & ~REV_OUT_SEL_SET) & ~REV_IN_SEL_SET) & ~XOR_OUT_SEL_SET) | POLY_SEL_SET)… in CRC_CalcBlockCRC()
82 …CRC->CSR = (CRC->CSR | REV_OUT_SEL_SET | REV_IN_SEL_SET | XOR_OUT_SEL_SET | POLY_SEL_SET) & ~TYPE_… in CRC_CalcBlockCRC()
88 …CRC->CSR = ((((CRC->CSR & ~REV_OUT_SEL_SET) & ~REV_IN_SEL_SET) & ~XOR_OUT_SEL_SET) | POLY_SEL_SET)… in CRC_CalcBlockCRC()
108 … CRC->CSR = CRC->CSR | REV_OUT_SEL_SET | REV_IN_SEL_SET | XOR_OUT_SEL_SET | TYPE_SEL_SET; in CRC_CalcBlockCRC()
114 … CRC->CSR = (((CRC->CSR & ~REV_OUT_SEL_SET) & ~REV_IN_SEL_SET) & ~XOR_OUT_SEL_SET) | TYPE_SEL_SET ; in CRC_CalcBlockCRC()
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/
A Dht32f1xxxx_usbd.c419 USBEPn->CSR = (USBEPn->CSR) & (DTGTX | DTGRX | NAKRX); in USBD_EPTReset()
511 USBEPn->CSR = (~(USBEPn->CSR)) & (STLTX | STLRX); in USBD_EPTSetHalt()
519 USBEPn->CSR = (~(USBEPn->CSR)) & STLTX; in USBD_EPTSetHalt()
524 USBEPn->CSR = (~(USBEPn->CSR)) & STLRX; in USBD_EPTSetHalt()
542 USBEPn->CSR = (USBEPn->CSR) & (STLTX | STLRX); in USBD_EPTClearHalt()
548 USBEPn->CSR = (USBEPn->CSR) & STLTX; in USBD_EPTClearHalt()
553 USBEPn->CSR = (USBEPn->CSR) & STLRX; in USBD_EPTClearHalt()
591 USBEPn->CSR = (USBEPn->CSR) & (DTGTX | DTGRX); in USBD_EPTClearDTG()
597 USBEPn->CSR = (USBEPn->CSR) & DTGTX; in USBD_EPTClearDTG()
602 USBEPn->CSR = (USBEPn->CSR) & DTGRX; in USBD_EPTClearDTG()
[all …]
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/
A Dht32f5xxxx_usbd.c430 USBEPn->CSR = (USBEPn->CSR) & (DTGTX | DTGRX | NAKRX); in USBD_EPTReset()
522 USBEPn->CSR = (~(USBEPn->CSR)) & (STLTX | STLRX); in USBD_EPTSetHalt()
530 USBEPn->CSR = (~(USBEPn->CSR)) & STLTX; in USBD_EPTSetHalt()
535 USBEPn->CSR = (~(USBEPn->CSR)) & STLRX; in USBD_EPTSetHalt()
553 USBEPn->CSR = (USBEPn->CSR) & (STLTX | STLRX); in USBD_EPTClearHalt()
559 USBEPn->CSR = (USBEPn->CSR) & STLTX; in USBD_EPTClearHalt()
564 USBEPn->CSR = (USBEPn->CSR) & STLRX; in USBD_EPTClearHalt()
602 USBEPn->CSR = (USBEPn->CSR) & (DTGTX | DTGRX); in USBD_EPTClearDTG()
608 USBEPn->CSR = (USBEPn->CSR) & DTGTX; in USBD_EPTClearDTG()
613 USBEPn->CSR = (USBEPn->CSR) & DTGRX; in USBD_EPTClearDTG()
[all …]
A Dht32f66xxx_cordic.c135 HT_CORDIC->CSR &= ~(CORDIC_CSR_FUNC_MASK | CORDIC_CSR_PRECISION_MASK | CORDIC_CSR_SCALE_MASK | \ in CORDIC_Init()
138 …HT_CORDIC->CSR |= (CORDIC_InitStruct->Function | CORDIC_InitStruct->Precision | CORDIC_InitStruct-… in CORDIC_Init()
154 HT_CORDIC->CSR |= CORDIC_CSR_IEN; in CORDIC_IntCmd()
158 HT_CORDIC->CSR &= ~CORDIC_CSR_IEN; in CORDIC_IntCmd()
179 HT_CORDIC->CSR |= CORDIC_DMA; in CORDIC_PDMACmd()
183 HT_CORDIC->CSR &= ~CORDIC_DMA; in CORDIC_PDMACmd()
193 if ((HT_CORDIC->CSR & CORDIC_FLAG_RRDY) != (u32)RESET) in CORDIC_GetFlagStatus_RRDY()
/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/
A Dald_usb.c218 USB0->CSR[ep_idx - 1].TXxMAXP = p_max; in ald_usb_dev_ep_config()
228 USB0->CSR[ep_idx - 1].RXxMAXP = p_max; in ald_usb_dev_ep_config()
503 USB0->CSR[ep_idx - 1].RXxCSRH = (uint8_t)((USB0->CSR[ep_idx - 1].RXxCSRH & in ald_usb_host_ep_data_toggle()
508 USB0->CSR[ep_idx - 1].TXxCSRH = (uint8_t)((USB0->CSR[ep_idx - 1].TXxCSRH & in ald_usb_host_ep_data_toggle()
526 USB0->CSR[ep_idx - 1].TXxCSRL &= ~flags; in ald_usb_host_ep_status_clear()
527 USB0->CSR[ep_idx - 1].RXxCSRL &= ~flags; in ald_usb_host_ep_status_clear()
723 USB0->CSR[ep_idx - 1].TXxTYPE |= tmp; in ald_usb_host_ep_speed_set()
725 USB0->CSR[ep_idx - 1].RXxTYPE |= tmp; in ald_usb_host_ep_speed_set()
766 return USB0->CSR[ep_idx - 1].RXxCOUNT; in ald_usb_ep_data_avail()
793 i = USB0->CSR[ep_idx - 1].RXxCOUNT; in ald_usb_ep_data_get()
[all …]
A Dald_cmu.c197 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) in ald_cmu_irq_handler()
198 || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) in ald_cmu_irq_handler()
210 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))) in ald_cmu_irq_handler()
238 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) in ald_cmu_irq_handler()
286 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config_default()
332 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config()
360 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config()
382 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config()
401 MODIFY_REG(CMU->CSR, CMU_CSR_CFT_CMD_MSK, 0xAA << CMU_CSR_CFT_CMD_POSS); in ald_cmu_clock_config()
403 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config()
[all …]
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_lptmr.h179 uint32_t reg = base->CSR; in LPTMR_EnableInterrupts()
184 base->CSR = reg; in LPTMR_EnableInterrupts()
196 uint32_t reg = base->CSR; in LPTMR_DisableInterrupts()
201 base->CSR = reg; in LPTMR_DisableInterrupts()
214 return (base->CSR & LPTMR_CSR_TIE_MASK); in LPTMR_GetEnabledInterrupts()
230 base->CSR |= LPTMR_CSR_TDRE_MASK; in LPTMR_EnableTimerDMA()
266 base->CSR |= mask; in LPTMR_ClearStatusFlags()
335 uint32_t reg = base->CSR; in LPTMR_StartTimer()
340 base->CSR = reg; in LPTMR_StartTimer()
352 uint32_t reg = base->CSR; in LPTMR_StopTimer()
[all …]
A Dfsl_mmdvsq.c19 temp = base->CSR; in MMDVSQ_GetDivideRemainder()
24 base->CSR = temp; in MMDVSQ_GetDivideRemainder()
30 base->CSR |= MMDVSQ_CSR_SRT_MASK; in MMDVSQ_GetDivideRemainder()
40 temp = base->CSR; in MMDVSQ_GetDivideQuotient()
45 base->CSR = temp; in MMDVSQ_GetDivideQuotient()
51 base->CSR |= MMDVSQ_CSR_SRT_MASK; in MMDVSQ_GetDivideQuotient()
A Dfsl_mmdvsq.h116 return (mmdvsq_execution_status_t)(base->CSR >> MMDVSQ_CSR_SQRT_SHIFT); in MMDVSQ_GetExecutionStatus()
137 base->CSR |= MMDVSQ_CSR_DFS_MASK; in MMDVSQ_SetFastStartConfig()
141 base->CSR &= ~MMDVSQ_CSR_DFS_MASK; in MMDVSQ_SetFastStartConfig()
162 base->CSR |= MMDVSQ_CSR_DZE_MASK; in MMDVSQ_SetDivideByZeroConfig()
166 base->CSR &= ~MMDVSQ_CSR_DZE_MASK; in MMDVSQ_SetDivideByZeroConfig()
/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/
A Dhal_rtc.c63 RTC->CSR |= RTC_CSR_CNF; in RTC_EnterConfigMode()
73 RTC->CSR &= ~RTC_CSR_CNF; in RTC_ExitConfigMode()
74 while (!(RTC->CSR & RTC_CSR_RTOFF)); in RTC_ExitConfigMode()
150 while (!(RTC->CSR & RTC_CSR_RTOFF)); in RTC_WaitForLastTask()
163 RTC->CSR &= ~RTC_CSR_RSF; in RTC_WaitForSynchro()
164 while (!(RTC->CSR & RTC_CSR_RSF)); in RTC_WaitForSynchro()
180 return (FlagStatus)(RTC->CSR & flag); in RTC_GetFlagStatus()
196 RTC->CSR &= ~flag; in RTC_ClearFlag()
210 return (ITStatus)(RTC->CSR & it); in RTC_GetITStatus()
225 RTC->CSR &= ~it; in RTC_ClearITPendingBit()
A Dhal_bkp.c85 (state) ? SET_BIT(BKP->CSR, BKP_CSR_TPIE) : CLEAR_BIT(BKP->CSR, BKP_CSR_TPIE); in BKP_ITConfig()
124 return ((BKP->CSR & BKP_CSR_TEF) ? SET : RESET); in BKP_GetFlagStatus()
134 SET_BIT(BKP->CSR, BKP_CSR_CTE); in BKP_ClearFlag()
144 return ((BKP->CSR & BKP_CSR_TIF) ? SET : RESET); in BKP_GetITStatus()
154 SET_BIT(BKP->CSR, BKP_CSR_CTI); in BKP_ClearITPendingBit()
/bsp/frdm-k64f/device/MK64F12/
A Dfsl_lptmr.h201 uint32_t reg = base->CSR; in LPTMR_EnableInterrupts()
206 base->CSR = reg; in LPTMR_EnableInterrupts()
218 uint32_t reg = base->CSR; in LPTMR_DisableInterrupts()
223 base->CSR = reg; in LPTMR_DisableInterrupts()
236 return (base->CSR & LPTMR_CSR_TIE_MASK); in LPTMR_GetEnabledInterrupts()
256 return (base->CSR & LPTMR_CSR_TCF_MASK); in LPTMR_GetStatusFlags()
268 base->CSR |= mask; in LPTMR_ClearStatusFlags()
337 uint32_t reg = base->CSR; in LPTMR_StartTimer()
342 base->CSR = reg; in LPTMR_StartTimer()
354 uint32_t reg = base->CSR; in LPTMR_StopTimer()
[all …]
A Dfsl_edma.c116 base->TCD[channel].CSR = 0; in EDMA_InstallTCD()
117 base->TCD[channel].CSR = tcd->CSR; in EDMA_InstallTCD()
200 … base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); in EDMA_SetBandWidth()
275 tcd->CSR = DMA_CSR_DREQ(true); in EDMA_TcdReset()
315 tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; in EDMA_TcdSetTransferConfig()
391 tcd->CSR |= DMA_CSR_INTMAJOR_MASK; in EDMA_TcdEnableInterrupts()
397 tcd->CSR |= DMA_CSR_INTHALF_MASK; in EDMA_TcdEnableInterrupts()
520 tcdRegs->CSR = 0; in EDMA_CreateHandle()
639 if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0)) in EDMA_SubmitTransfer()
707 tcdRegs->CSR = csr; in EDMA_SubmitTransfer()
[all …]
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/inc/
A Dhk32f0xx_divsqrt.h41 #define DVSQ_EnableDivFastStart() DVSQ->CSR &= ~DIVSQRT_CSR_DFS /* 使能快速启动…
42 #define DVSQ_DisableDivFastStart() DVSQ->CSR |= DIVSQRT_CSR_DFS /* 关闭快速启动…
45 #define DVSQ_ConfigDivUnsigned() DVSQ->CSR |= DIVSQRT_CSR_UNSIGN_DIV /* 将DVSQ配…
46 #define DVSQ_ConfigDivSigned() DVSQ->CSR &= ~DIVSQRT_CSR_UNSIGN_DIV /* 将DVSQ配…
49 #define DVSQ_ConfigSqrtPresHigh() DVSQ->CSR |= DIVSQRT_CSR_HPRESQRT /* 配置DVSQ为…
50 #define DVSQ_ConfigSqrtPresNormal() DVSQ->CSR &= ~DIVSQRT_CSR_HPRESQRT /* 配置DVSQ…
53 #define DVSQ_StartDivCalc() DVSQ->CSR |= DIVSQRT_CSR_DIV_SRT /* 开始除法运算…
56 #define DVSQ_IsBusy() ((DVSQ->CSR & DIVSQRT_CSR_BUSY)? 1:0) /* 返回'1'表…
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/
A Dfm33lc0xx_fl_uart.h367 SET_BIT(UARTx->CSR, UART_CSR_TXIREN_Msk); in FL_UART_EnableIRModulation()
378 CLEAR_BIT(UARTx->CSR, UART_CSR_TXIREN_Msk); in FL_UART_DisableIRModulation()
400 SET_BIT(UARTx->CSR, UART_CSR_RXTOEN_Msk); in FL_UART_EnableRXTimeout()
411 CLEAR_BIT(UARTx->CSR, UART_CSR_RXTOEN_Msk); in FL_UART_DisableRXTimeout()
433 SET_BIT(UARTx->CSR, UART_CSR_IOSWAP_Msk); in FL_UART_EnablePinSwap()
467 SET_BIT(UARTx->CSR, UART_CSR_NEWUP_Msk); in FL_UART_EnableFallingEdgeWakeup()
478 CLEAR_BIT(UARTx->CSR, UART_CSR_NEWUP_Msk); in FL_UART_DisableFallingEdgeWakeup()
696 SET_BIT(UARTx->CSR, UART_CSR_RXEN_Msk); in FL_UART_EnableRX()
707 CLEAR_BIT(UARTx->CSR, UART_CSR_RXEN_Msk); in FL_UART_DisableRX()
729 SET_BIT(UARTx->CSR, UART_CSR_TXEN_Msk); in FL_UART_EnableTX()
[all …]
A Dfm33lc0xx_fl_lpuart.h275 MODIFY_REG(LPUARTx->CSR, LPUART_CSR_WKBYTE_CFG_Msk, mode); in FL_LPUART_SetRXWakeupMode()
304 MODIFY_REG(LPUARTx->CSR, LPUART_CSR_RXEV_Msk, event); in FL_LPUART_SetWakeup()
330 SET_BIT(LPUARTx->CSR, LPUART_CSR_IOSWAP_Msk); in FL_LPUART_EnablePinSwap()
341 CLEAR_BIT(LPUARTx->CSR, LPUART_CSR_IOSWAP_Msk); in FL_LPUART_DisablePinSwap()
480 MODIFY_REG(LPUARTx->CSR, LPUART_CSR_PARITY_Msk, parity); in FL_LPUART_SetParity()
508 MODIFY_REG(LPUARTx->CSR, LPUART_CSR_RXPOL_Msk, polarity); in FL_LPUART_SetRXPolarity()
535 MODIFY_REG(LPUARTx->CSR, LPUART_CSR_TXPOL_Msk, polarity); in FL_LPUART_SetTXPolarity()
559 SET_BIT(LPUARTx->CSR, LPUART_CSR_RXEN_Msk); in FL_LPUART_EnableRX()
581 CLEAR_BIT(LPUARTx->CSR, LPUART_CSR_RXEN_Msk); in FL_LPUART_DisableRX()
592 SET_BIT(LPUARTx->CSR, LPUART_CSR_TXEN_Msk); in FL_LPUART_EnableTX()
[all …]
/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/
A Dald_cmu.c107 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 3) in ald_cmu_irq_handler()
108 || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) in ald_cmu_irq_handler()
122 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 3))) in ald_cmu_irq_handler()
141 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 3) in ald_cmu_irq_handler()
205 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config_default()
255 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config()
277 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config()
313 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config()
342 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config()
372 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config()
[all …]
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_ll_opamp.h391 MODIFY_REG(OPAMP->CSR, OPAMP_CSR_AOP_RANGE, PowerRange); in LL_OPAMP_SetCommonPowerRange()
410 return (uint32_t)(READ_BIT(OPAMP->CSR, OPAMP_CSR_AOP_RANGE)); in LL_OPAMP_GetCommonPowerRange()
435 MODIFY_REG(OPAMP->CSR, in LL_OPAMP_SetPowerMode()
487 CLEAR_BIT(OPAMP->CSR, in LL_OPAMP_SetMode()
511 return (uint32_t)(((READ_BIT(OPAMP->CSR, in LL_OPAMP_GetMode()
533 MODIFY_REG(OPAMP->CSR, in LL_OPAMP_SetFunctionalMode()
579 MODIFY_REG(OPAMP->CSR, in LL_OPAMP_SetInputNonInverting()
601 uint32_t input_non_inverting_opamp_x = READ_BIT(OPAMP->CSR, in LL_OPAMP_GetInputNonInverting()
627 MODIFY_REG(OPAMP->CSR, in LL_OPAMP_SetInputInverting()
647 uint32_t input_inverting_opamp_x = READ_BIT(OPAMP->CSR, in LL_OPAMP_GetInputInverting()
[all …]
A Dstm32l1xx_ll_comp.h346 MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WNDWE, WindowMode); in LL_COMP_SetCommonWindowMode()
361 return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WNDWE)); in LL_COMP_GetCommonWindowMode()
385 MODIFY_REG(COMP->CSR, COMP_CSR_SPEED, PowerMode); in LL_COMP_SetPowerMode()
400 return (uint32_t)(READ_BIT(COMP->CSR, COMP_CSR_SPEED)); in LL_COMP_GetPowerMode()
568 MODIFY_REG(COMP->CSR, in LL_COMP_SetInputMinus()
596 return (uint32_t)((READ_BIT(COMP->CSR, COMP_CSR_INSEL) * __COMP_IS_INSTANCE_EVEN(COMPx)) in LL_COMP_GetInputMinus()
622 MODIFY_REG(COMP->CSR, in LL_COMP_SetInputPullingResistor()
690 MODIFY_REG(COMP->CSR, in LL_COMP_SetOutputSelection()
720 return (uint32_t)((READ_BIT(COMP->CSR, COMP_CSR_OUTSEL) * __COMP_IS_INSTANCE_EVEN(COMPx)) in LL_COMP_GetOutputSelection()
752 SET_BIT(COMP->CSR, __COMP_IS_INSTANCE_ODD(COMPx) << LL_COMP_ENABLE_COMP1_BITOFFSET_POS); in LL_COMP_Enable()
[all …]
A Dstm32l1xx_ll_rcc.h668 SET_BIT(RCC->CSR, RCC_CSR_LSEON); in LL_RCC_LSE_Enable()
678 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); in LL_RCC_LSE_Disable()
688 SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); in LL_RCC_LSE_EnableBypass()
698 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); in LL_RCC_LSE_DisableBypass()
709 SET_BIT(RCC->CSR, RCC_CSR_LSECSSON); in LL_RCC_LSE_EnableCSS()
762 SET_BIT(RCC->CSR, RCC_CSR_LSION); in LL_RCC_LSI_Enable()
772 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); in LL_RCC_LSI_Disable()
1113 SET_BIT(RCC->CSR, RCC_CSR_RTCEN); in LL_RCC_EnableRTC()
1123 CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN); in LL_RCC_DisableRTC()
1143 SET_BIT(RCC->CSR, RCC_CSR_RTCRST); in LL_RCC_ForceBackupDomainReset()
[all …]
A Dstm32l1xx_ll_pwr.h485 SET_BIT(PWR->CSR, WakeUpPin); in LL_PWR_EnableWakeUpPin()
503 CLEAR_BIT(PWR->CSR, WakeUpPin); in LL_PWR_DisableWakeUpPin()
521 return ((READ_BIT(PWR->CSR, WakeUpPin) == WakeUpPin) ? 1UL : 0UL); in LL_PWR_IsEnabledWakeUpPin()
602 return ((READ_BIT(PWR->CSR, PWR_CSR_WUF) == PWR_CSR_WUF) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU()
612 return ((READ_BIT(PWR->CSR, PWR_CSR_SBF) == PWR_CSR_SBF) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SB()
623 return ((READ_BIT(PWR->CSR, PWR_CSR_PVDO) == PWR_CSR_PVDO) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
635 return ((READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == PWR_CSR_VREFINTRDYF) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VREFINTRDY()
645 return ((READ_BIT(PWR->CSR, PWR_CSR_VOSF) == PWR_CSR_VOSF) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VOS()
655 return ((READ_BIT(PWR->CSR, PWR_CSR_REGLPF) == PWR_CSR_REGLPF) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGLPF()
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/
A Dstm32l1xx_hal_opamp_ex.c163 CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS); in HAL_OPAMPEx_SelfCalibrateAll()
203 CLEAR_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD_ALL); in HAL_OPAMPEx_SelfCalibrateAll()
223 MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_L_ALL, in HAL_OPAMPEx_SelfCalibrateAll()
241 MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H_ALL, in HAL_OPAMPEx_SelfCalibrateAll()
362 CLEAR_BIT (OPAMP->CSR, (OPAMP_CSR_OPAXCAL_H_ALL | in HAL_OPAMPEx_SelfCalibrateAll()
368 SET_BIT(OPAMP->CSR, tmp_OpaxSwitchesContextBackup); in HAL_OPAMPEx_SelfCalibrateAll()
540 CLEAR_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD_ALL); in HAL_OPAMPEx_SelfCalibrateAll()
558 MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_L_ALL, in HAL_OPAMPEx_SelfCalibrateAll()
574 MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H_ALL, in HAL_OPAMPEx_SelfCalibrateAll()
674 CLEAR_BIT (OPAMP->CSR, (OPAMP_CSR_OPAXCAL_H_ALL | in HAL_OPAMPEx_SelfCalibrateAll()
[all …]
/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/
A Dft32f0xx_comp.c28 COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */ in COMP_DeInit()
65 tmpreg = COMP->CSR; in COMP_Init()
75 COMP->CSR = tmpreg; in COMP_Init()
145 COMP->CSR |= (uint32_t) (1<<COMP_Selection); in COMP_Cmd()
150 COMP->CSR &= (uint32_t)(~((uint32_t)1<<COMP_Selection)); in COMP_Cmd()
202 if ((COMP->CSR & (COMP_CSR_COMP1OUT<<COMP_Selection)) != 0) in COMP_GetOutputLevel()
251 COMP->CSR |= (uint32_t) COMP_CSR_WNDWEN; in COMP_WindowCmd()
256 COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWEN); in COMP_WindowCmd()
282 COMP->CSR |= (uint32_t) (COMP_CSR_NCOMPLOCK<<COMP_Selection); in COMP_LockConfig()
/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/
A Dald_cmu.c181 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) in ald_cmu_irq_handler()
182 || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) in ald_cmu_irq_handler()
194 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))) in ald_cmu_irq_handler()
222 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) in ald_cmu_irq_handler()
223 || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) in ald_cmu_irq_handler()
269 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config_default()
311 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config()
339 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config()
361 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config()
380 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); in ald_cmu_clock_config()
[all …]
/bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/
A Dhal_comp.c14 COMPx->CSR[channel] = COMP_CSR_OFLT(init->OutFilter) in COMP_Init()
31 COMPx->CSR[channel] |= COMP_CSR_EN_MASK; in COMP_Enable()
35 COMPx->CSR[channel] &= ~COMP_CSR_EN_MASK; in COMP_Enable()
44 COMPx->CSR[channel] |= COMP_CSR_LOCK_MASK; in COMP_Lock()
52 if ( 0u != ( COMP_CSR_OUT_MASK & COMPx->CSR[channel] ) ) in COMP_GetOutputStatus()

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