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Searched refs:CSR_MIDELEG (Results 1 – 13 of 13) sorted by relevance

/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/
A Dhpm_interrupt.h102 set_csr(CSR_MIDELEG, mask); in delegate_irq()
112 clear_csr(CSR_MIDELEG, mask); in undelegate_irq()
A Dhpm_csr_regs.h35 #define CSR_MIDELEG (0x303) macro
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/
A Dhpm_interrupt.h102 set_csr(CSR_MIDELEG, mask); in delegate_irq()
112 clear_csr(CSR_MIDELEG, mask); in undelegate_irq()
A Dhpm_csr_regs.h35 #define CSR_MIDELEG (0x303) macro
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/
A Dhpm_interrupt.h102 set_csr(CSR_MIDELEG, mask); in delegate_irq()
112 clear_csr(CSR_MIDELEG, mask); in undelegate_irq()
A Dhpm_csr_regs.h35 #define CSR_MIDELEG (0x303) macro
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/
A Dhpm_interrupt.h102 set_csr(CSR_MIDELEG, mask); in delegate_irq()
112 clear_csr(CSR_MIDELEG, mask); in undelegate_irq()
A Dhpm_csr_regs.h35 #define CSR_MIDELEG (0x303) macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/
A Dcsr.h154 #define CSR_MIDELEG 0x303 macro
/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/drivers/
A Driscv_encoding.h739 #define CSR_MIDELEG 0x303 macro
1203 DECLARE_CSR(mideleg, CSR_MIDELEG)
/bsp/hifive1/freedom-e-sdk/bsp/env/
A Dencoding.h719 #define CSR_MIDELEG 0x303 macro
1155 DECLARE_CSR(mideleg, CSR_MIDELEG)
/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/
A Dencoding.h719 #define CSR_MIDELEG 0x303 macro
1155 DECLARE_CSR(mideleg, CSR_MIDELEG)
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/
A Dhpm_csr_regs.h35 #define CSR_MIDELEG (0x303) macro

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