Home
last modified time | relevance | path

Searched refs:CSR_MIE (Results 1 – 20 of 20) sorted by relevance

/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/
A Dhpm_interrupt.h66 set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in enable_irq_from_intc()
75 clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in disable_irq_from_intc()
83 set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in enable_mchtmr_irq()
92 clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in disable_mchtmr_irq()
118 set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_enable_swi()
128 clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_disable_swi()
A Dhpm_csr_regs.h36 #define CSR_MIE (0x304) macro
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/
A Dhpm_interrupt.h66 set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in enable_irq_from_intc()
75 clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in disable_irq_from_intc()
83 set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in enable_mchtmr_irq()
92 clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in disable_mchtmr_irq()
118 set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_enable_swi()
128 clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_disable_swi()
A Dhpm_csr_regs.h23 #define CSR_MIE (0x304) macro
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/
A Dhpm_interrupt.h66 set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in enable_irq_from_intc()
75 clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in disable_irq_from_intc()
83 set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in enable_mchtmr_irq()
92 clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in disable_mchtmr_irq()
118 set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_enable_swi()
128 clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_disable_swi()
A Dhpm_csr_regs.h23 #define CSR_MIE (0x304) macro
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/
A Dhpm_interrupt.h66 set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in enable_irq_from_intc()
75 clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in disable_irq_from_intc()
83 set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in enable_mchtmr_irq()
92 clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in disable_mchtmr_irq()
208 set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_enable_swi()
218 clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_disable_swi()
A Dhpm_csr_regs.h36 #define CSR_MIE (0x304) macro
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/
A Dhpm_interrupt.h66 set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in enable_irq_from_intc()
75 clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in disable_irq_from_intc()
83 set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in enable_mchtmr_irq()
92 clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in disable_mchtmr_irq()
208 set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_enable_swi()
218 clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_disable_swi()
A Dhpm_csr_regs.h36 #define CSR_MIE (0x304) macro
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/
A Dhpm_interrupt.h66 set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in enable_irq_from_intc()
75 clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in disable_irq_from_intc()
83 set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in enable_mchtmr_irq()
92 clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in disable_mchtmr_irq()
208 set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_enable_swi()
218 clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_disable_swi()
A Dhpm_csr_regs.h36 #define CSR_MIE (0x304) macro
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/
A Dhpm_interrupt.h66 set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in enable_irq_from_intc()
75 clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); in disable_irq_from_intc()
83 set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in enable_mchtmr_irq()
92 clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); in disable_mchtmr_irq()
208 set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_enable_swi()
218 clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); in intc_m_disable_swi()
A Dhpm_csr_regs.h36 #define CSR_MIE (0x304) macro
/bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/
A Dcore-v-mcu.c242 val = csr_read(CSR_MIE); in system_init()
303 RegReadVal = csr_read(CSR_MIE); in undefined_handler()
307 csr_read_clear(CSR_MIE, BIT(mcause)); in undefined_handler()
/bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/
A Dcsr.h30 #define CSR_MIE 0x304 macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/
A Dcsr.h155 #define CSR_MIE 0x304 macro
/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/drivers/
A Driscv_encoding.h740 #define CSR_MIE 0x304 macro
1204 DECLARE_CSR(mie, CSR_MIE)
/bsp/hifive1/freedom-e-sdk/bsp/env/
A Dencoding.h720 #define CSR_MIE 0x304 macro
1156 DECLARE_CSR(mie, CSR_MIE)
/bsp/sparkfun-redv/freedom-e-sdk/bsp/env/
A Dencoding.h720 #define CSR_MIE 0x304 macro
1156 DECLARE_CSR(mie, CSR_MIE)

Completed in 159 milliseconds