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Searched refs:CSR_OFFSET (Results 1 – 16 of 16) sorted by relevance

/bsp/airm2m/air32f103/libraries/AIR32F10xLib/src/
A Dair32f10x_bkp.c38 #define CSR_OFFSET (BKP_OFFSET + 0x34) macro
40 #define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
44 #define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
48 #define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
A Dair32f10x_cec.c44 #define CSR_OFFSET (CEC_OFFSET + 0x10) macro
46 #define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
50 #define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
A Dair32f10x_pwr.c39 #define CSR_OFFSET (PWR_OFFSET + 0x04) macro
41 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
A Dair32f10x_rcc_ex.c63 #define CSR_OFFSET (RCC_OFFSET + 0x24) macro
65 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
A Dair32f10x_rcc.c65 #define CSR_OFFSET (RCC_OFFSET + 0x24) macro
67 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
/bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/src/
A DHAL_bkp.c63 #define CSR_OFFSET (BKP_OFFSET + 0x34) macro
65 #define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
69 #define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
73 #define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
A DHAL_pwr.c63 #define CSR_OFFSET (PWR_OFFSET + 0x04) macro
65 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
A DHAL_rcc.c84 #define CSR_OFFSET (RCC_OFFSET + 0x24) macro
86 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/
A DHAL_bkp.c63 #define CSR_OFFSET (BKP_OFFSET + 0x34) macro
65 #define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
69 #define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
73 #define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
A DHAL_pwr.c63 #define CSR_OFFSET (PWR_OFFSET + 0x04) macro
65 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
A DHAL_rcc.c84 #define CSR_OFFSET (RCC_OFFSET + 0x24) macro
86 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
/bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/StdPeriph_Driver/src/
A Dch32f10x_pwr.c26 #define CSR_OFFSET (PWR_OFFSET + 0x04) macro
28 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
/bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/src/
A DHAL_pwr.c63 #define CSR_OFFSET (PWR_OFFSET + 0x04) macro
65 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
A DHAL_rcc.c84 #define CSR_OFFSET (RCC_OFFSET + 0x24) macro
86 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
/bsp/tkm32F499/Libraries/Hal_lib/src/
A DHAL_pwr.c63 #define CSR_OFFSET (PWR_OFFSET + 0x04) macro
65 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
A DHAL_rcc.c86 #define CSR_OFFSET (RCC_OFFSET + 0x24) macro
88 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))

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