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Searched refs:CTL0 (Results 1 – 25 of 26) sorted by relevance

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/bsp/nuvoton/libraries/ma35/rtt_port/
A Ddrv_sys_i2c0.c36 I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_SI; in I2C0_MasterRx()
42 I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_SI; in I2C0_MasterRx()
58 I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_SI; in I2C0_MasterRx()
63 I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_SI; in I2C0_MasterRx()
69 I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | (I2C_CTL_STO | I2C_CTL_SI); in I2C0_MasterRx()
84 I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_SI; in I2C0_MasterTx()
90 I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_SI; in I2C0_MasterTx()
103 I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_SI; in I2C0_MasterTx()
136 I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_STA; in ma35d1_write_i2c_data()
177 I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_STA; in ma35d1_read_i2c_data()
[all …]
A Ddrv_i2c.c138 while (!(bus->I2C->CTL0 & I2C_CTL0_SI_Msk)) in nu_i2c_wait_ready_with_timeout()
266 nu_i2c->I2C->CTL0 |= I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk; in nu_i2c_mst_xfer()
331 if (nu_i2c->I2C->CTL0 & I2C_CTL_AA) in nu_i2c_mst_xfer()
A Ddrv_ecap.c196 if ((psNuEcap->base->CTL0 & (ECAP_CHANNEL_MSK << ECAP_CTL0_CAPIEN0_Pos)) != 0U) in nu_ecap_open()
217 if ((psNuEcap->base->CTL0 & (ECAP_CHANNEL_MSK << ECAP_CTL0_CAPIEN0_Pos)) == 0U) in nu_ecap_close()
A Ddrv_i2s.c541 if (!(psNuI2s->i2s_base->CTL0 & (I2S_CTL0_TXEN_Msk | I2S_CTL0_RXEN_Msk))) in nu_i2s_stop()
/bsp/renesas/rzn2l_etherkit/rzn/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c286 R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
288 R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
290 if (1 != R_CLMA0->CTL0) in bsp_clock_init()
309 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
311 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
313 if (1 != R_CLMA1->CTL0) in bsp_clock_init()
332 R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
334 R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
336 if (1 != R_CLMA2->CTL0) in bsp_clock_init()
355 R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
[all …]
A Dbsp_module_stop.h197 … channel) ? R_CLMA0->CTL0 : ((1 >= \
198 … channel) ? R_CLMA1->CTL0 : ((2 >= \
201CTL0 : \
203CTL0));
/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c286 R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
288 R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
290 if (1 != R_CLMA0->CTL0) in bsp_clock_init()
309 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
311 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
313 if (1 != R_CLMA1->CTL0) in bsp_clock_init()
332 R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
334 R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
336 if (1 != R_CLMA2->CTL0) in bsp_clock_init()
355 R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
[all …]
A Dbsp_module_stop.h197 … channel) ? R_CLMA0->CTL0 : ((1 >= \
198 … channel) ? R_CLMA1->CTL0 : ((2 >= \
201CTL0 : \
203CTL0));
/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c318 R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
320 R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
322 if (1 != R_CLMA0->CTL0) in bsp_clock_init()
341 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
343 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
345 if (1 != R_CLMA1->CTL0) in bsp_clock_init()
364 R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
366 R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
368 if (1 != R_CLMA2->CTL0) in bsp_clock_init()
387 R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; in bsp_clock_init()
[all …]
A Dbsp_module_stop.h197 … channel) ? R_CLMA0->CTL0 : ((1 >= \
198 … channel) ? R_CLMA1->CTL0 : ((2 >= \
201CTL0 : \
203CTL0));
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_lvb_drv.c93 ptr->TX_PHY[tx_index].CTL0 = (ptr->TX_PHY[tx_index].CTL0 & ~(LVB_TX_PHY_CTL0_TX_IDLE_MASK | in lvb_lvds_phy_lane_init()
107 ptr->TX_PHY[tx_index].CTL0 |= (1ul<<7); in lvb_lvds_phy_lane_init()
109 ptr->TX_PHY[tx_index].CTL0 &= ~(1ul<<7); in lvb_lvds_phy_lane_init()
/bsp/nuvoton/libraries/m031/rtt_port/
A Ddrv_i2c.c108 while (!(bus->I2C->CTL0 & I2C_CTL0_SI_Msk)) in nu_i2c_wait_ready_with_timeout()
181 nu_i2c->I2C->CTL0 |= I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk; in nu_i2c_mst_xfer()
246 if (nu_i2c->I2C->CTL0 & I2C_CTL_AA) in nu_i2c_mst_xfer()
/bsp/nuvoton/libraries/m460/rtt_port/
A Ddrv_i2c.c129 while (!(bus->I2C->CTL0 & I2C_CTL0_SI_Msk)) in nu_i2c_wait_ready_with_timeout()
257 nu_i2c->I2C->CTL0 |= I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk; in nu_i2c_mst_xfer()
322 if (nu_i2c->I2C->CTL0 & I2C_CTL_AA) in nu_i2c_mst_xfer()
A Ddrv_i2s.c540 if (!(psNuI2s->i2s_base->CTL0 & (I2S_CTL0_TXEN_Msk | I2S_CTL0_RXEN_Msk))) in nu_i2s_stop()
/bsp/nuvoton/libraries/nuc980/rtt_port/
A Ddrv_i2c.c136 while (!(bus->I2C->CTL0 & I2C_CTL0_SI_Msk)) in nu_i2c_wait_ready_with_timeout()
264 nu_i2c->I2C->CTL0 |= I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk; in nu_i2c_mst_xfer()
329 if (nu_i2c->I2C->CTL0 & I2C_CTL_AA) in nu_i2c_mst_xfer()
/bsp/nuvoton/libraries/m480/rtt_port/
A Ddrv_i2c.c117 while (!(bus->I2C->CTL0 & I2C_CTL0_SI_Msk)) in nu_i2c_wait_ready_with_timeout()
245 nu_i2c->I2C->CTL0 |= I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk; in nu_i2c_mst_xfer()
310 if (nu_i2c->I2C->CTL0 & I2C_CTL_AA) in nu_i2c_mst_xfer()
A Ddrv_i2s.c504 if (!(psNuI2s->i2s_base->CTL0 & (I2S_CTL0_TXEN_Msk | I2S_CTL0_RXEN_Msk))) in nu_i2s_stop()
/bsp/nuvoton/libraries/m2354/rtt_port/
A Ddrv_i2c.c117 while (!(bus->I2C->CTL0 & I2C_CTL0_SI_Msk)) in nu_i2c_wait_ready_with_timeout()
245 nu_i2c->I2C->CTL0 |= I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk; in nu_i2c_mst_xfer()
310 if (nu_i2c->I2C->CTL0 & I2C_CTL_AA) in nu_i2c_mst_xfer()
A Ddrv_i2s.c504 if (!(psNuI2s->i2s_base->CTL0 & (I2S_CTL0_TXEN_Msk | I2S_CTL0_RXEN_Msk))) in nu_i2s_stop()
/bsp/nuvoton/numaker-m467hj/board/
A Dboard_dev.c203 EBI->CTL0 |= EBI_CTL_CACCESS_Msk; in rt_hw_ssd1963_port()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/
A Dhpm_lvb_regs.h18 __RW uint32_t CTL0; /* 0x1C: TX PHY Setting */ member
/bsp/nuvoton/numaker-pfm-m487/board/
A Dboard_dev.c288 EBI->CTL0 |= EBI_CTL0_CACCESS_Msk; in rt_hw_ili9341_port()
/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR9A07G074.h14293 …__IOM uint8_t CTL0; /*!< (@ 0x00000000) CLMA Control Register 0 … member
A DR9A07G075.h21986 …__IOM uint8_t CTL0; /*!< (@ 0x00000000) CLMA Control Register 0 … member
/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR9A07G084.h27689 …__IOM uint8_t CTL0; /*!< (@ 0x00000000) CLMA Control Register 0 … member

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