| /bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ |
| A D | ht32f1xxxx_mctm.c | 206 MCTMx->CTR |= CTR_COMPRE; in MCTM_COMPRECmd()
211 MCTMx->CTR &= ~CTR_COMPRE; in MCTM_COMPRECmd()
234 MCTMx->CTR |= CTR_COMUS; in MCTM_COMUSConfig()
239 MCTMx->CTR &= ~CTR_COMUS; in MCTM_COMUSConfig()
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| A D | ht32f1xxxx_tm.c | 431 TMx->CTR |= CTR_TME; in TM_Cmd()
436 TMx->CTR &= ~CTR_TME; in TM_Cmd()
763 TMx->CTR |= CTR_CRBE; in TM_CRRPreloadCmd()
768 TMx->CTR &= ~CTR_CRBE; in TM_CRRPreloadCmd()
1550 TMx->CTR |= CTR_CHCCDS; in TM_CHCCDSConfig()
1554 TMx->CTR &= ~CTR_CHCCDS; in TM_CHCCDSConfig()
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| /bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ |
| A D | ht32f5xxxx_mctm.c | 219 MCTMx->CTR |= CTR_COMPRE; in MCTM_COMPRECmd()
224 MCTMx->CTR &= ~CTR_COMPRE; in MCTM_COMPRECmd()
247 MCTMx->CTR |= CTR_COMUS; in MCTM_COMUSConfig()
252 MCTMx->CTR &= ~CTR_COMUS; in MCTM_COMUSConfig()
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| A D | ht32f5xxxx_tm.c | 506 TMx->CTR |= CTR_TME; in TM_Cmd()
511 TMx->CTR &= ~CTR_TME; in TM_Cmd()
856 TMx->CTR |= CTR_CRBE; in TM_CRRPreloadCmd()
861 TMx->CTR &= ~CTR_CRBE; in TM_CRRPreloadCmd()
1749 TMx->CTR |= CTR_CHCCDS; in TM_CHCCDSConfig()
1753 TMx->CTR &= ~CTR_CHCCDS; in TM_CHCCDSConfig()
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| /bsp/microchip/same54/bsp/hal/documentation/ |
| A D | aes_sync.rst | 14 The driver supports ECB/CBC/CFB/OFB/CTR mode for data encryption, and GCM/CCM
29 * Counter (CTR)
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| /bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/ |
| A D | ht32f1xxxx_01.h | 702 …__IO uint32_t CTR; /*!< 0x010 Control Register …
871 …__IO uint32_t CTR; /*!< 0x010 Control Register …
915 …__IO uint32_t CTR; /*!< 0x010 Control Register … member
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| /bsp/microchip/same54/ |
| A D | README_zh.md | 84 - Five confidential modes of operation (ECB, CBC, CFB, OFB, CTR)
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| A D | README.md | 84 - Five confidential modes of operation (ECB, CBC, CFB, OFB, CTR)
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| /bsp/microchip/samd51-adafruit-metro-m4/ |
| A D | README_zh.md | 91 - Five confidential modes of operation (ECB, CBC, CFB, OFB, CTR)
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| A D | README.md | 91 - Five confidential modes of operation (ECB, CBC, CFB, OFB, CTR)
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| /bsp/microchip/samd51-seeed-wio-terminal/ |
| A D | README.md | 94 - Five confidential modes of operation (ECB, CBC, CFB, OFB, CTR)
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| A D | README_zh.md | 94 - Five confidential modes of operation (ECB, CBC, CFB, OFB, CTR)
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| /bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/ |
| A D | ht32f5xxxx_01.h | 1075 …__IO uint32_t CTR; /*!< 0x010 Control Register … member
1258 …__IO uint32_t CTR; /*!< 0x010 Control Register …
1302 …__IO uint32_t CTR; /*!< 0x010 Control Register … member
1530 …__IO uint32_t CTR; /*!< 0x010 Control Register … member
1581 …__IO uint32_t CTR; /*!< 0x010 Control Register … member
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| /bsp/microchip/same70/bsp/same70b/include/component/ |
| A D | aes.h | 497 … uint32_t CTR:32; /**< bit: 0..31 GCM Encryption Counter */ member
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| /bsp/synwit/libraries/SWM320_CSL/CMSIS/CoreSupport/ |
| A D | core_cm7.h | 433 …__I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register … member
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| /bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/ |
| A D | core_cm7.h | 483 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ member
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| /bsp/samd21/sam_d2x_asflib/CMSIS/Include/ |
| A D | core_cm7.h | 433 …__I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register … member
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| /bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/ |
| A D | core_cm7.h | 483 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ member
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| /bsp/mm32l3xx/Libraries/CMSIS/IAR_CORE/ |
| A D | core_cm7.h | 433 …__I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register … member
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| /bsp/synwit/libraries/SWM341_CSL/CMSIS/CoreSupport/ |
| A D | core_cm7.h | 483 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ member
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| /bsp/mm32l07x/Libraries/CMSIS/IAR_CORE/ |
| A D | core_cm7.h | 433 …__I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register … member
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| /bsp/tae32f5300/Libraries/CMSIS/Include/ |
| A D | core_cm7.h | 483 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ member
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| /bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | core_cm7.h | 483 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ member
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| /bsp/renesas/ra8m1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | core_cm7.h | 483 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ member
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| /bsp/renesas/ra8d1-vision-board/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | core_cm7.h | 483 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ member
|