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Searched refs:CTRL0 (Results 1 – 25 of 48) sorted by relevance

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/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_opamp_drv.h180 opamp->CTRL0 |= OPAMP_CTRL0_EN_LV_MASK; in opamp_enable()
201 opamp->CTRL0 &= ~OPAMP_CTRL0_EN_LV_MASK; in opamp_disable()
223 …opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_MILLER_SEL_MASK)) | OPAMP_CTRL0_MILLER_SEL_SET(select… in opamp_miller_cap_select()
245 opamp->CTRL0 &= ~OPAMP_CTRL0_DISABLE_PM_CAP_MASK; in opamp_phase_margin_cap_enable()
266 opamp->CTRL0 |= OPAMP_CTRL0_DISABLE_PM_CAP_MASK; in opamp_phase_margin_cap_disable()
288 opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_VIM_SEL_MASK)) | OPAMP_CTRL0_VIM_SEL_SET(select); in opamp_inn_pad_select()
312 opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_GAIN_SEL_MASK)) | OPAMP_CTRL0_GAIN_SEL_SET(select); in opamp_gain_select()
335 opamp->CTRL0 |= OPAMP_CTRL0_VBYPASS_MASK; in opamp_disconnect_vssa()
356 opamp->CTRL0 &= ~OPAMP_CTRL0_VBYPASS_MASK; in opamp_connect_vssa()
378 opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_VIP_SEL_MASK)) | OPAMP_CTRL0_VIP_SEL_SET(select); in opamp_inp_pad_select()
[all …]
A Dhpm_ptpc_drv.h82 … ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) in ptpc_set_ns_counter_rollover()
94 ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK; in ptpc_enable_capture_keep()
105 ptr->PTPC[index].CTRL0 &= ~PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK; in ptpc_disable_capture_keep()
117 ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) in ptpc_set_ns_counter_update_type()
195 ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_COMP_EN_MASK; in ptpc_config_compare()
231 ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK; in ptpc_enable_timer()
242 ptr->PTPC[index].CTRL0 &= ~PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK; in ptpc_disable_timer()
255 ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~(PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK in ptpc_config_capture()
A Dhpm_ewdg_drv.h256 return ((ptr->CTRL0 & EWDG_CTRL0_CFG_LOCK_MASK) != 0U); in ewdg_is_ctrl_reg_locked()
268 return (1UL << EWDG_CTRL0_DIV_VALUE_GET(ptr->CTRL0)); in ewdg_get_count_clk_divider()
281 return ((ptr->CTRL0 & EWDG_CTRL0_REF_LOCK_MASK) != 0U); in ewdg_is_refresh_locked()
358 return (ewdg_refresh_unlock_method_t) (EWDG_CTRL0_REF_UNLOCK_MEC_GET(ptr->CTRL0)); in ewdg_get_refresh_unlock_method()
/bsp/Vango/v85xx/Libraries/VangoV85xx_standard_peripheral/Source/
A Dlib_u32k.c32 U32Kx->CTRL0 &= ~U32K_CTRL0_EN; in U32K_DeInit()
36 U32Kx->CTRL0 = U32K_CTRL0_RSTValue; in U32K_DeInit()
88 tmp_reg1 = U32Kx->CTRL0; in U32K_Init()
99 U32Kx->CTRL0 = tmp_reg1; in U32K_Init()
260 tmp = U32Kx->CTRL0; in U32K_Cmd()
266 U32Kx->CTRL0 = tmp; in U32K_Cmd()
311 tmp = U32Kx->CTRL0; in U32K_WKUModeConfig()
314 U32Kx->CTRL0 = tmp; in U32K_WKUModeConfig()
/bsp/Vango/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/
A Dlib_u32k.c31 U32Kx->CTRL0 &= ~U32K_CTRL0_EN; in U32K_DeInit()
35 U32Kx->CTRL0 = U32K_CTRL0_RSTValue; in U32K_DeInit()
83 tmp_reg1 = U32Kx->CTRL0; in U32K_Init()
92 U32Kx->CTRL0 = tmp_reg1; in U32K_Init()
251 tmp = U32Kx->CTRL0; in U32K_Cmd()
257 U32Kx->CTRL0 = tmp; in U32K_Cmd()
303 tmp = U32Kx->CTRL0; in U32K_WKUModeConfig()
306 U32Kx->CTRL0 = tmp; in U32K_WKUModeConfig()
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_ptpc_drv.c39 ptr->PTPC[index].CTRL0 = PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(config->ns_rollover_mode) in ptpc_init()
62 …if ((PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(ptr->PTPC[index].CTRL0) == ptpc_ns_counter_rollov… in ptpc_set_ns_update()
76 ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK; in ptpc_update_timer()
84 ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_INIT_TIMER_MASK; in ptpc_init_timer()
93 ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_INIT_TIMER_MASK; in ptpc_init_timer_with_initial()
102 …if (PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(ptr->PTPC[index].CTRL0) == ptpc_ns_counter_rollove… in ptpc_set_pps()
A Dhpm_ewdg_drv.c183 ptr->CTRL0 = ctrl0; in ewdg_init_ctrl_func()
457 uint32_t ctrl0 = ptr->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK; in ewdg_switch_clock_source()
468 ptr->CTRL0 = ctrl0; in ewdg_switch_clock_source()
A Dhpm_opamp_drv.c6 opamp->CTRL0 = 0; in opamp_init()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/
A Dhpm_enet_soc_drv.h68 …HPM_CONCTL->CTRL0 &= ~(CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK | CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MA… in enet_rgmii_set_clock_delay()
69 …HPM_CONCTL->CTRL0 |= CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SET(tx_delay) | CONCTL_CTRL0_ENET0_RXCLK_DLY… in enet_rgmii_set_clock_delay()
71 …HPM_CONCTL->CTRL0 &= ~(CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK | CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MA… in enet_rgmii_set_clock_delay()
72 …HPM_CONCTL->CTRL0 |= CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SET(tx_delay) | CONCTL_CTRL0_ENET1_RXCLK_DLY… in enet_rgmii_set_clock_delay()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/
A Dhpm_clock_drv.c205 if (EWDG_CTRL0_CLK_SEL_GET(s_wdgs[instance]->CTRL0) == 0) { in get_frequency_for_ewdg()
217 if (EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0) == 0) { in get_frequency_for_pewdg()
259 clk_src_index = EWDG_CTRL0_CLK_SEL_GET(s_wdgs[node_or_instance]->CTRL0); in clock_get_source()
264 clk_src_index = EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0); in clock_get_source()
353 …HPM_PEWDG->CTRL0 = (HPM_PEWDG->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SEL_SET(wdg_clk_… in clock_set_wdg_source()
361 …s_wdgs[instance]->CTRL0 = (s_wdgs[instance]->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SE… in clock_set_wdg_source()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/
A Dhpm_clock_drv.c246 if (EWDG_CTRL0_CLK_SEL_GET(s_wdgs[instance]->CTRL0) == 0) { in get_frequency_for_ewdg()
257 if (EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0) == 0) { in get_frequency_for_pewdg()
292 clk_src_index = EWDG_CTRL0_CLK_SEL_GET(s_wdgs[node_or_instance]->CTRL0); in clock_get_source()
297 clk_src_index = EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0); in clock_get_source()
370 …HPM_PEWDG->CTRL0 = (HPM_PEWDG->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SEL_SET(wdg_clk_… in clock_set_wdg_source()
378 …s_wdgs[instance]->CTRL0 = (s_wdgs[instance]->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SE… in clock_set_wdg_source()
A Dhpm_enet_soc_drv.h61 ptr->CTRL0 &= ~(ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK | ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK); in enet_rgmii_set_clock_delay()
62 …ptr->CTRL0 |= ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SET(tx_delay) | ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SET(rx… in enet_rgmii_set_clock_delay()
/bsp/apollo2/libraries/drivers/hal/
A Dam_hal_ctimer.c190 ui32TimerASrc = AM_BFX(CTIMER, CTRL0, TMRA0CLK, *pui32ConfigReg) - in ctimer_source_hfrc()
191 AM_ENUMX(CTIMER, CTRL0, TMRA0CLK, HFRC_DIV4); in ctimer_source_hfrc()
192 ui32TimerBSrc = AM_BFX(CTIMER, CTRL0, TMRB0CLK, *pui32ConfigReg) - in ctimer_source_hfrc()
193 AM_ENUMX(CTIMER, CTRL0, TMRB0CLK, HFRC_DIV4); in ctimer_source_hfrc()
198 if ( (ui32TimerASrc <= (AM_ENUMX(CTIMER, CTRL0, TMRA0CLK, HFRC_DIV4K) - in ctimer_source_hfrc()
199 AM_ENUMX(CTIMER, CTRL0, TMRA0CLK, HFRC_DIV4))) || in ctimer_source_hfrc()
200 (ui32TimerBSrc <= (AM_ENUMX(CTIMER, CTRL0, TMRB0CLK, HFRC_DIV4K) - in ctimer_source_hfrc()
201 AM_ENUMX(CTIMER, CTRL0, TMRB0CLK, HFRC_DIV4))) ) in ctimer_source_hfrc()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/
A Dhpm_clock_drv.c233 if (EWDG_CTRL0_CLK_SEL_GET(s_wdgs[instance]->CTRL0) == 0) { in get_frequency_for_ewdg()
245 if (EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0) == 0) { in get_frequency_for_pewdg()
280 clk_src_index = EWDG_CTRL0_CLK_SEL_GET(s_wdgs[node_or_instance]->CTRL0); in clock_get_source()
285 clk_src_index = EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0); in clock_get_source()
407 …HPM_PEWDG->CTRL0 = (HPM_PEWDG->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SEL_SET(wdg_clk_… in clock_set_wdg_source()
415 …s_wdgs[instance]->CTRL0 = (s_wdgs[instance]->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SE… in clock_set_wdg_source()
A Dhpm_enet_soc_drv.h61 ptr->CTRL0 &= ~(ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK | ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK); in enet_rgmii_set_clock_delay()
62 …ptr->CTRL0 |= ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SET(tx_delay) | ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SET(rx… in enet_rgmii_set_clock_delay()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/
A Dhpm_clock_drv.c243 if (EWDG_CTRL0_CLK_SEL_GET(s_wdgs[instance]->CTRL0) == 0) { in get_frequency_for_ewdg()
255 if (EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0) == 0) { in get_frequency_for_pewdg()
303 clk_src_index = EWDG_CTRL0_CLK_SEL_GET(s_wdgs[node_or_instance]->CTRL0); in clock_get_source()
308 clk_src_index = EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0); in clock_get_source()
417 …HPM_PEWDG->CTRL0 = (HPM_PEWDG->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SEL_SET(wdg_clk_… in clock_set_wdg_source()
425 …s_wdgs[instance]->CTRL0 = (s_wdgs[instance]->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SE… in clock_set_wdg_source()
/bsp/asm9260t/platform/
A Duart.c30 …uartBase->CTRL0[R_CLR] = ASM_UART_CTRL0_SFTRST | ASM_UART_CTRL0_CLKGATE | ASM_UART_CTRL0_RXTO_ENAB… in Hw_UartReset()
31 …uartBase->CTRL0[R_SET] = ASM_UART_CTRL0_SFTRST | ASM_UART_CTRL0_CLKGATE | ASM_UART_CTRL0_RXTO_ENAB… in Hw_UartReset()
A Duart.h20 volatile rt_uint32_t CTRL0[4]; member
/bsp/rm48x50/HALCoGen/include/
A Dreg_crc.h39 uint32 CTRL0; /**< 0x0000: Global Control Register 0 >**/ member
/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/
A Dn32g4fr_qspi.c138 QSPI->CTRL0 = tmpregister; in QspiInitConfig()
152 QSPI->CTRL0 = tmpregister; in QspiInitConfig()
/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/
A Dn32g45x_qspi.c138 QSPI->CTRL0 = tmpregister; in QspiInitConfig()
152 QSPI->CTRL0 = tmpregister; in QspiInitConfig()
/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/
A Dn32g45x_qspi.c143 QSPI->CTRL0 = tmpregister; in QspiInitConfig()
157 QSPI->CTRL0 = tmpregister; in QspiInitConfig()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/
A Dhpm_opamp_regs.h13 __RW uint32_t CTRL0; /* 0x0: control reg */ member
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/
A Dhpm_conctl_regs.h13 __RW uint32_t CTRL0; /* 0x0: */ member
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/
A Dhpm_ewdg_regs.h13 __RW uint32_t CTRL0; /* 0x0: wdog ctrl register 0 member

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