| /bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/ |
| A D | n32l40x_spi.c | 79 #define CTRL1_CLR_MASK ((uint16_t)0x3040) macro
180 tmpregister &= CTRL1_CLR_MASK; in SPI_Init()
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| A D | n32l40x_usart.c | 67 #define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */ macro
212 tmpregister &= CTRL1_CLR_MASK; in USART_Init()
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| A D | n32l40x_i2c.c | 100 #define CTRL1_CLR_MASK ((uint16_t)0xFBF5) macro
297 tmpregister &= CTRL1_CLR_MASK; in I2C_Init()
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| A D | n32l40x_adc.c | 81 #define CTRL1_CLR_MASK ((uint32_t)0xFFF0FEFF) macro
230 tmpreg1 &= CTRL1_CLR_MASK; in ADC_Init()
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| /bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/ |
| A D | n32l43x_spi.c | 79 #define CTRL1_CLR_MASK ((uint16_t)0x3040) macro
180 tmpregister &= CTRL1_CLR_MASK; in SPI_Init()
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| A D | n32l43x_usart.c | 67 #define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */ macro
212 tmpregister &= CTRL1_CLR_MASK; in USART_Init()
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| A D | n32l43x_i2c.c | 100 #define CTRL1_CLR_MASK ((uint16_t)0xFBF5) macro
297 tmpregister &= CTRL1_CLR_MASK; in I2C_Init()
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| A D | n32l43x_adc.c | 81 #define CTRL1_CLR_MASK ((uint32_t)0xFFF0FEFF) macro
230 tmpreg1 &= CTRL1_CLR_MASK; in ADC_Init()
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| /bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/ |
| A D | n32g4fr_spi.c | 79 #define CTRL1_CLR_MASK ((uint16_t)0x3040) macro
189 tmpregister &= CTRL1_CLR_MASK; in SPI_Init()
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| A D | n32g4fr_usart.c | 67 #define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */ macro
225 tmpregister &= CTRL1_CLR_MASK; in USART_Init()
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| A D | n32g4fr_i2c.c | 100 #define CTRL1_CLR_MASK ((uint16_t)0xFBF5) macro
320 tmpregister &= CTRL1_CLR_MASK; in I2C_Init()
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| /bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/ |
| A D | n32wb452_spi.c | 79 #define CTRL1_CLR_MASK ((uint16_t)0x3040) macro
189 tmpregister &= CTRL1_CLR_MASK; in SPI_Init()
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| A D | n32wb452_usart.c | 67 #define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */ macro
225 tmpregister &= CTRL1_CLR_MASK; in USART_Init()
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| A D | n32wb452_i2c.c | 100 #define CTRL1_CLR_MASK ((uint16_t)0xFBF5) macro
320 tmpregister &= CTRL1_CLR_MASK; in I2C_Init()
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| /bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/ |
| A D | n32g43x_spi.c | 79 #define CTRL1_CLR_MASK ((uint16_t)0x3040) macro
180 tmpregister &= CTRL1_CLR_MASK; in SPI_Init()
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| A D | n32g43x_usart.c | 67 #define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */ macro
212 tmpregister &= CTRL1_CLR_MASK; in USART_Init()
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| A D | n32g43x_i2c.c | 100 #define CTRL1_CLR_MASK ((uint16_t)0xFBF5) macro
297 tmpregister &= CTRL1_CLR_MASK; in I2C_Init()
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| A D | n32g43x_adc.c | 81 #define CTRL1_CLR_MASK ((uint32_t)0xFFF0FEFF) macro
230 tmpreg1 &= CTRL1_CLR_MASK; in ADC_Init()
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| /bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/ |
| A D | n32g45x_spi.c | 79 #define CTRL1_CLR_MASK ((uint16_t)0x3040) macro
189 tmpregister &= CTRL1_CLR_MASK; in SPI_Init()
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| A D | n32g45x_usart.c | 67 #define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */ macro
225 tmpregister &= CTRL1_CLR_MASK; in USART_Init()
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| A D | n32g45x_i2c.c | 100 #define CTRL1_CLR_MASK ((uint16_t)0xFBF5) macro
320 tmpregister &= CTRL1_CLR_MASK; in I2C_Init()
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| A D | n32g45x_adc.c | 81 #define CTRL1_CLR_MASK ((uint32_t)0xFFF0FEFF) macro
253 tmpreg1 &= CTRL1_CLR_MASK; in ADC_Init()
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| /bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/ |
| A D | n32g45x_spi.c | 79 #define CTRL1_CLR_MASK ((uint16_t)0x3040) macro
189 tmpregister &= CTRL1_CLR_MASK; in SPI_Init()
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| A D | n32g45x_usart.c | 67 #define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */ macro
225 tmpregister &= CTRL1_CLR_MASK; in USART_Init()
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| A D | n32g45x_i2c.c | 100 #define CTRL1_CLR_MASK ((uint16_t)0xFBF5) macro
297 tmpregister &= CTRL1_CLR_MASK; in I2C_Init()
|