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Searched refs:CTRLC (Results 1 – 25 of 31) sorted by relevance

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/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/
A Dslcd.h350 SLCD->CTRLC.reg |= SLCD_CTRLC_LOCK; in slcd_lock_shadow_memory()
360 SLCD->CTRLC.reg &= (SLCD_CTRLC_MASK & ( ~SLCD_CTRLC_LOCK)); in slcd_unlock_shadow_memory()
370 SLCD->CTRLC.reg |= SLCD_CTRLC_CLEAR; in slcd_clear_display_memory()
667 SLCD->CTRLC.reg |= SLCD_CTRLC_ACMEN; in slcd_enable_automated_character()
677 SLCD->CTRLC.reg &= ~SLCD_CTRLC_ACMEN; in slcd_disable_automated_character()
697 SLCD->CTRLC.reg |= SLCD_CTRLC_ABMEN; in slcd_enable_automated_bit()
707 SLCD->CTRLC.reg &= ~SLCD_CTRLC_ABMEN; in slcd_disable_automated_bit()
A Dslcd.c167 SLCD->CTRLC.reg |= SLCD_CTRLC_LPPM(CONF_SLCD_POWER_MODE) | SLCD_CTRLC_CTST(0x0F); in slcd_init()
260 uint16_t temp = SLCD->CTRLC.reg; in slcd_set_contrast()
265 SLCD->CTRLC.reg = temp; in slcd_set_contrast()
/bsp/microchip/samc21/bsp/hri/
A Dhri_adc_c21.h1289 tmp = ((Adc *)hw)->CTRLC.reg; in hri_adc_get_CTRLC_DIFFMODE_bit()
1298 tmp = ((Adc *)hw)->CTRLC.reg; in hri_adc_write_CTRLC_DIFFMODE_bit()
1301 ((Adc *)hw)->CTRLC.reg = tmp; in hri_adc_write_CTRLC_DIFFMODE_bit()
1333 tmp = ((Adc *)hw)->CTRLC.reg; in hri_adc_get_CTRLC_LEFTADJ_bit()
1342 tmp = ((Adc *)hw)->CTRLC.reg; in hri_adc_write_CTRLC_LEFTADJ_bit()
1345 ((Adc *)hw)->CTRLC.reg = tmp; in hri_adc_write_CTRLC_LEFTADJ_bit()
1377 tmp = ((Adc *)hw)->CTRLC.reg; in hri_adc_get_CTRLC_FREERUN_bit()
1386 tmp = ((Adc *)hw)->CTRLC.reg; in hri_adc_write_CTRLC_FREERUN_bit()
1389 ((Adc *)hw)->CTRLC.reg = tmp; in hri_adc_write_CTRLC_FREERUN_bit()
1421 tmp = ((Adc *)hw)->CTRLC.reg; in hri_adc_get_CTRLC_CORREN_bit()
[all …]
A Dhri_tsens_c21.h530 tmp = ((Tsens *)hw)->CTRLC.reg; in hri_tsens_get_CTRLC_FREERUN_bit()
539 tmp = ((Tsens *)hw)->CTRLC.reg; in hri_tsens_write_CTRLC_FREERUN_bit()
542 ((Tsens *)hw)->CTRLC.reg = tmp; in hri_tsens_write_CTRLC_FREERUN_bit()
570 tmp = ((Tsens *)hw)->CTRLC.reg; in hri_tsens_get_CTRLC_WINMODE_bf()
579 tmp = ((Tsens *)hw)->CTRLC.reg; in hri_tsens_write_CTRLC_WINMODE_bf()
582 ((Tsens *)hw)->CTRLC.reg = tmp; in hri_tsens_write_CTRLC_WINMODE_bf()
603 tmp = ((Tsens *)hw)->CTRLC.reg; in hri_tsens_read_CTRLC_WINMODE_bf()
611 ((Tsens *)hw)->CTRLC.reg |= mask; in hri_tsens_set_CTRLC_reg()
618 tmp = ((Tsens *)hw)->CTRLC.reg; in hri_tsens_get_CTRLC_reg()
626 ((Tsens *)hw)->CTRLC.reg = data; in hri_tsens_write_CTRLC_reg()
[all …]
A Dhri_sdadc_c21.h1347 ((Sdadc *)hw)->CTRLC.reg |= SDADC_CTRLC_FREERUN; in hri_sdadc_set_CTRLC_FREERUN_bit()
1355 tmp = ((Sdadc *)hw)->CTRLC.reg; in hri_sdadc_get_CTRLC_FREERUN_bit()
1364 tmp = ((Sdadc *)hw)->CTRLC.reg; in hri_sdadc_write_CTRLC_FREERUN_bit()
1367 ((Sdadc *)hw)->CTRLC.reg = tmp; in hri_sdadc_write_CTRLC_FREERUN_bit()
1383 ((Sdadc *)hw)->CTRLC.reg ^= SDADC_CTRLC_FREERUN; in hri_sdadc_toggle_CTRLC_FREERUN_bit()
1391 ((Sdadc *)hw)->CTRLC.reg |= mask; in hri_sdadc_set_CTRLC_reg()
1400 tmp = ((Sdadc *)hw)->CTRLC.reg; in hri_sdadc_get_CTRLC_reg()
1408 ((Sdadc *)hw)->CTRLC.reg = data; in hri_sdadc_write_CTRLC_reg()
1416 ((Sdadc *)hw)->CTRLC.reg &= ~mask; in hri_sdadc_clear_CTRLC_reg()
1424 ((Sdadc *)hw)->CTRLC.reg ^= mask; in hri_sdadc_toggle_CTRLC_reg()
[all …]
A Dhri_sercom_c21.h4881 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_get_CTRLC_GTIME_bf()
4890 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_write_CTRLC_GTIME_bf()
4893 ((Sercom *)hw)->USART.CTRLC.reg = tmp; in hri_sercomusart_write_CTRLC_GTIME_bf()
4914 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_read_CTRLC_GTIME_bf()
4930 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_get_CTRLC_BRKLEN_bf()
4939 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_write_CTRLC_BRKLEN_bf()
4942 ((Sercom *)hw)->USART.CTRLC.reg = tmp; in hri_sercomusart_write_CTRLC_BRKLEN_bf()
4963 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_read_CTRLC_BRKLEN_bf()
4979 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_get_CTRLC_HDRDLY_bf()
4988 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_write_CTRLC_HDRDLY_bf()
[all …]
/bsp/microchip/saml10/bsp/hri/
A Dhri_adc_l10.h1289 tmp = ((Adc *)hw)->CTRLC.reg; in hri_adc_get_CTRLC_DIFFMODE_bit()
1298 tmp = ((Adc *)hw)->CTRLC.reg; in hri_adc_write_CTRLC_DIFFMODE_bit()
1301 ((Adc *)hw)->CTRLC.reg = tmp; in hri_adc_write_CTRLC_DIFFMODE_bit()
1333 tmp = ((Adc *)hw)->CTRLC.reg; in hri_adc_get_CTRLC_LEFTADJ_bit()
1342 tmp = ((Adc *)hw)->CTRLC.reg; in hri_adc_write_CTRLC_LEFTADJ_bit()
1345 ((Adc *)hw)->CTRLC.reg = tmp; in hri_adc_write_CTRLC_LEFTADJ_bit()
1377 tmp = ((Adc *)hw)->CTRLC.reg; in hri_adc_get_CTRLC_FREERUN_bit()
1386 tmp = ((Adc *)hw)->CTRLC.reg; in hri_adc_write_CTRLC_FREERUN_bit()
1389 ((Adc *)hw)->CTRLC.reg = tmp; in hri_adc_write_CTRLC_FREERUN_bit()
1421 tmp = ((Adc *)hw)->CTRLC.reg; in hri_adc_get_CTRLC_CORREN_bit()
[all …]
A Dhri_sercom_l10.h4990 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_get_CTRLC_INACK_bit()
4999 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_write_CTRLC_INACK_bit()
5002 ((Sercom *)hw)->USART.CTRLC.reg = tmp; in hri_sercomusart_write_CTRLC_INACK_bit()
5030 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_get_CTRLC_DSNACK_bit()
5039 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_write_CTRLC_DSNACK_bit()
5042 ((Sercom *)hw)->USART.CTRLC.reg = tmp; in hri_sercomusart_write_CTRLC_DSNACK_bit()
5071 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_get_CTRLC_GTIME_bf()
5080 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_write_CTRLC_GTIME_bf()
5083 ((Sercom *)hw)->USART.CTRLC.reg = tmp; in hri_sercomusart_write_CTRLC_GTIME_bf()
5104 tmp = ((Sercom *)hw)->USART.CTRLC.reg; in hri_sercomusart_read_CTRLC_GTIME_bf()
[all …]
A Dhri_nvmctrl_l10.h733 ((Nvmctrl *)hw)->CTRLC.reg |= NVMCTRL_CTRLC_MANW_Msk; in hri_nvmctrl_set_CTRLC_MANW_bit()
740 tmp = ((Nvmctrl *)hw)->CTRLC.reg; in hri_nvmctrl_get_CTRLC_MANW_bit()
749 tmp = ((Nvmctrl *)hw)->CTRLC.reg; in hri_nvmctrl_write_CTRLC_MANW_bit()
752 ((Nvmctrl *)hw)->CTRLC.reg = tmp; in hri_nvmctrl_write_CTRLC_MANW_bit()
766 ((Nvmctrl *)hw)->CTRLC.reg ^= NVMCTRL_CTRLC_MANW_Msk; in hri_nvmctrl_toggle_CTRLC_MANW_bit()
773 ((Nvmctrl *)hw)->CTRLC.reg |= mask; in hri_nvmctrl_set_CTRLC_reg()
780 tmp = ((Nvmctrl *)hw)->CTRLC.reg; in hri_nvmctrl_get_CTRLC_reg()
788 ((Nvmctrl *)hw)->CTRLC.reg = data; in hri_nvmctrl_write_CTRLC_reg()
795 ((Nvmctrl *)hw)->CTRLC.reg &= ~mask; in hri_nvmctrl_clear_CTRLC_reg()
802 ((Nvmctrl *)hw)->CTRLC.reg ^= mask; in hri_nvmctrl_toggle_CTRLC_reg()
[all …]
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_sercom_d51.h5016 tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; in hri_sercomi2cm_get_CTRLC_DATA32B_bit()
5025 tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; in hri_sercomi2cm_write_CTRLC_DATA32B_bit()
5028 ((Sercom *)hw)->I2CM.CTRLC.reg = tmp; in hri_sercomi2cm_write_CTRLC_DATA32B_bit()
5229 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_get_CTRLC_DATA32B_bit()
5238 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_write_CTRLC_DATA32B_bit()
5241 ((Sercom *)hw)->SPI.CTRLC.reg = tmp; in hri_sercomspi_write_CTRLC_DATA32B_bit()
5270 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_get_CTRLC_ICSPACE_bf()
5279 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_write_CTRLC_ICSPACE_bf()
5282 ((Sercom *)hw)->SPI.CTRLC.reg = tmp; in hri_sercomspi_write_CTRLC_ICSPACE_bf()
5303 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_read_CTRLC_ICSPACE_bf()
[all …]
/bsp/microchip/same54/bsp/hri/
A Dhri_sercom_e54.h5016 tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; in hri_sercomi2cm_get_CTRLC_DATA32B_bit()
5025 tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; in hri_sercomi2cm_write_CTRLC_DATA32B_bit()
5028 ((Sercom *)hw)->I2CM.CTRLC.reg = tmp; in hri_sercomi2cm_write_CTRLC_DATA32B_bit()
5229 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_get_CTRLC_DATA32B_bit()
5238 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_write_CTRLC_DATA32B_bit()
5241 ((Sercom *)hw)->SPI.CTRLC.reg = tmp; in hri_sercomspi_write_CTRLC_DATA32B_bit()
5270 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_get_CTRLC_ICSPACE_bf()
5279 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_write_CTRLC_ICSPACE_bf()
5282 ((Sercom *)hw)->SPI.CTRLC.reg = tmp; in hri_sercomspi_write_CTRLC_ICSPACE_bf()
5303 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_read_CTRLC_ICSPACE_bf()
[all …]
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_sercom_d51.h5016 tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; in hri_sercomi2cm_get_CTRLC_DATA32B_bit()
5025 tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; in hri_sercomi2cm_write_CTRLC_DATA32B_bit()
5028 ((Sercom *)hw)->I2CM.CTRLC.reg = tmp; in hri_sercomi2cm_write_CTRLC_DATA32B_bit()
5229 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_get_CTRLC_DATA32B_bit()
5238 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_write_CTRLC_DATA32B_bit()
5241 ((Sercom *)hw)->SPI.CTRLC.reg = tmp; in hri_sercomspi_write_CTRLC_DATA32B_bit()
5270 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_get_CTRLC_ICSPACE_bf()
5279 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_write_CTRLC_ICSPACE_bf()
5282 ((Sercom *)hw)->SPI.CTRLC.reg = tmp; in hri_sercomspi_write_CTRLC_ICSPACE_bf()
5303 tmp = ((Sercom *)hw)->SPI.CTRLC.reg; in hri_sercomspi_read_CTRLC_ICSPACE_bf()
[all …]
/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/
A Dusart.c247 usart_hw->CTRLC.reg = ((usart_hw->CTRLC.reg) & SERCOM_USART_CTRLC_GTIME_Msk) in _usart_set_config()
277 usart_hw->CTRLC.reg &= ~(SERCOM_USART_CTRLC_GTIME(0x7)); in _usart_set_config()
278 usart_hw->CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(config->rs485_guard_time); in _usart_set_config()
285 usart_hw->CTRLC.reg = ctrlc; in _usart_set_config()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/
A Dtsens_callback.c157 if(!(TSENS->CTRLC.reg & TSENS_CTRLC_FREERUN)) { in tsens_read_job()
A Dtsens.c84 TSENS->CTRLC.reg = in _tsens_set_config()
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/
A Dtc.h613 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ member
637 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ member
659 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ member
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/
A Dtc.h616 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ member
640 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ member
662 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ member
/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/
A Dadc.c211 adc_module->CTRLC.reg = window_mode; in adc_set_window_mode()
581 adc_module->CTRLC.reg = in _adc_set_config()
655 adc_module->CTRLC.reg |= config->window.window_mode; in _adc_set_config()
A Dadc_feature.h724 master_inst->hw->CTRLC.reg |= dualsel; in adc_set_master_slave_mode()
/bsp/microchip/samc21/bsp/samc21/include/component/
A Dsdadc.h442 uint32_t CTRLC:1; /*!< bit: 2 CTRLC Synchronization Busy */ member
582 __IO SDADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 8) Control C */ member
A Dadc.h589 uint16_t CTRLC:1; /*!< bit: 3 CTRLC Synchronization Busy */ member
702 __IO ADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 16) Control C */ member
/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/
A Dsdadc.c142 sdadc_module->CTRLC.reg = in _sdadc_set_config()
/bsp/microchip/same54/bsp/include/component/
A Dsercom.h1576 __IO SERCOM_I2CM_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) I2CM Control C */ member
1600 __IO SERCOM_I2CS_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) I2CS Control C */ member
1622 __IO SERCOM_SPI_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) SPI Control C */ member
1647 __IO SERCOM_USART_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) USART Control C */ member
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Dsercom.h1576 __IO SERCOM_I2CM_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) I2CM Control C */ member
1600 __IO SERCOM_I2CS_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) I2CS Control C */ member
1622 __IO SERCOM_SPI_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) SPI Control C */ member
1647 __IO SERCOM_USART_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) USART Control C */ member
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Dsercom.h1576 __IO SERCOM_I2CM_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) I2CM Control C */ member
1600 __IO SERCOM_I2CS_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) I2CS Control C */ member
1622 __IO SERCOM_SPI_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) SPI Control C */ member
1647 __IO SERCOM_USART_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) USART Control C */ member

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