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Searched refs:CTRLR0 (Results 1 – 8 of 8) sorted by relevance

/bsp/ck802/libraries/common/spi/
A Ddw_spi.c418 uint16_t temp = addr->CTRLR0; in dw_spi_set_datawidth()
462 addr->CTRLR0 &= (~DW_SPI_POLARITY); in dw_spi_set_polarity()
466 addr->CTRLR0 |= DW_SPI_POLARITY; in dw_spi_set_polarity()
486 addr->CTRLR0 &= (~DW_SPI_PHASE); in dw_spi_set_phase()
490 addr->CTRLR0 |= DW_SPI_PHASE; in dw_spi_set_phase()
521 addr->CTRLR0 &= (~DW_SPI_TMOD_BIT8); in dw_spi_set_mode()
522 addr->CTRLR0 &= (~DW_SPI_TMOD_BIT9); in dw_spi_set_mode()
526 addr->CTRLR0 |= DW_SPI_TMOD_BIT8; in dw_spi_set_mode()
532 addr->CTRLR0 |= DW_SPI_TMOD_BIT9; in dw_spi_set_mode()
536 addr->CTRLR0 |= DW_SPI_TMOD_BIT8; in dw_spi_set_mode()
[all …]
A Ddw_spi.h118 __IOM uint16_t CTRLR0; /* Offset: 0x000 (R/W) Control register 0 */ member
/bsp/airm2m/air105/libraries/HAL_Driver/Src/
A Dcore_spi.c422 SPI->CTRLR0 = ctrl; in SPI_MasterInit()
1132 SPI->CTRLR0 &= ~(SPI_CTRLR0_SCPOL|SPI_CTRLR0_SCPH); in SPI_SetNewConfig()
1138 SPI->CTRLR0 |= SPI_CTRLR0_SCPH; in SPI_SetNewConfig()
1141 SPI->CTRLR0 |= SPI_CTRLR0_SCPOL; in SPI_SetNewConfig()
1144 SPI->CTRLR0 |= SPI_CTRLR0_SCPOL|SPI_CTRLR0_SCPH; in SPI_SetNewConfig()
/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/
A Dbsp_module_stop.h207 #define BSP_MSTP_DMY_FSP_IP_SHOSTIF(channel) R_SHOSTIF->CTRLR0;
/bsp/airm2m/air105/libraries/HAL_Driver/Inc/
A Dair105.h313 __IO uint16_t CTRLR0; member
/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR9A07G074.h11460 …__IOM uint32_t CTRLR0; /*!< (@ 0x00000000) Control Register 0 … member
/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR9A07G084.h25341 …__IOM uint32_t CTRLR0; /*!< (@ 0x00000000) Control Register 0 … member
/bsp/renesas/rzn2l_etherkit/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR9A07G084.h25341 …__IOM uint32_t CTRLR0; /*!< (@ 0x00000000) Control Register 0 … member

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