Home
last modified time | relevance | path

Searched refs:CYBSP_CSD_CLK_DIV_obj (Results 1 – 14 of 14) sorted by relevance

/bsp/Infineon/psoc6-cy8ckit-062s4/libs/TARGET_CY8CKIT-062S4/config/GeneratedSource/
A Dcycfg_clocks.c32 const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = variable
51 cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); in reserve_cycfg_clocks()
A Dcycfg_clocks.h50 extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
51 #define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj
/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/config/GeneratedSource/
A Dcycfg_clocks.c32 const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = variable
51 cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); in reserve_cycfg_clocks()
A Dcycfg_clocks.h50 extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
51 #define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj
/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/libs/TARGET_CY8CKIT-062-WIFI-BT/config/GeneratedSource/
A Dcycfg_clocks.h57 extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
58 #define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj
A Dcycfg_clocks.c38 const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = variable
70 cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); in reserve_cycfg_clocks()
/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/config/GeneratedSource/
A Dcycfg_clocks.h57 extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
58 #define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj
A Dcycfg_clocks.c38 const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = variable
70 cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); in reserve_cycfg_clocks()
/bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/config/GeneratedSource/
A Dcycfg_clocks.h57 extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
58 #define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj
A Dcycfg_clocks.c38 const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = variable
70 cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); in reserve_cycfg_clocks()
/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/config/GeneratedSource/
A Dcycfg_clocks.h57 extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
58 #define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj
A Dcycfg_clocks.c38 const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = variable
70 cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); in reserve_cycfg_clocks()
/bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/config/GeneratedSource/
A Dcycfg_clocks.h57 extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
58 #define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj
A Dcycfg_clocks.c38 const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = variable
70 cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); in reserve_cycfg_clocks()

Completed in 12 milliseconds