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Searched refs:CYBSP_SWDCK_PIN (Results 1 – 20 of 20) sorted by relevance

/bsp/Infineon/libraries/templates/XMC7200D/libs/TARGET_APP_KIT_XMC72_EVK/config/GeneratedSource/
A Dcycfg_pins.c183 .channel_num = CYBSP_SWDCK_PIN,
216 Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); in init_cycfg_pins()
A Dcycfg_pins.h216 #define CYBSP_SWDCK_PIN 5U macro
/bsp/Infineon/xmc7200-kit_xmc7200_evk/libs/TARGET_APP_KIT_XMC72_EVK/config/GeneratedSource/
A Dcycfg_pins.c183 .channel_num = CYBSP_SWDCK_PIN,
216 Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); in init_cycfg_pins()
A Dcycfg_pins.h216 #define CYBSP_SWDCK_PIN 5U macro
/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/
A Dcycfg_pins.c200 .channel_num = CYBSP_SWDCK_PIN,
235 Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); in init_cycfg_pins()
A Dcycfg_pins.h216 #define CYBSP_SWDCK_PIN 5U macro
/bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/config/GeneratedSource/
A Dcycfg_pins.c76 .channel_num = CYBSP_SWDCK_PIN,
300 Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); in init_cycfg_pins()
A Dcycfg_pins.h106 #define CYBSP_SWDCK_PIN 7U macro
/bsp/Infineon/psoc6-cy8ckit-062s4/libs/TARGET_CY8CKIT-062S4/config/GeneratedSource/
A Dcycfg_pins.c124 .channel_num = CYBSP_SWDCK_PIN,
324 Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); in init_cycfg_pins()
A Dcycfg_pins.h162 #define CYBSP_SWDCK_PIN 7U macro
/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/config/GeneratedSource/
A Dcycfg_pins.c124 .channel_num = CYBSP_SWDCK_PIN,
324 Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); in init_cycfg_pins()
A Dcycfg_pins.h132 #define CYBSP_SWDCK_PIN 7U macro
/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/libs/TARGET_CY8CKIT-062-WIFI-BT/config/GeneratedSource/
A Dcycfg_pins.c172 .channel_num = CYBSP_SWDCK_PIN,
421 Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); in init_cycfg_pins()
A Dcycfg_pins.h238 #define CYBSP_SWDCK_PIN 7U macro
239 #define CYBSP_J2_18_PIN CYBSP_SWDCK_PIN
/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/config/GeneratedSource/
A Dcycfg_pins.c172 .channel_num = CYBSP_SWDCK_PIN,
421 Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); in init_cycfg_pins()
A Dcycfg_pins.h254 #define CYBSP_SWDCK_PIN 7U macro
/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/config/GeneratedSource/
A Dcycfg_pins.c172 .channel_num = CYBSP_SWDCK_PIN,
421 Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); in init_cycfg_pins()
A Dcycfg_pins.h254 #define CYBSP_SWDCK_PIN 7U macro
/bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/config/GeneratedSource/
A Dcycfg_pins.c172 .channel_num = CYBSP_SWDCK_PIN,
421 Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); in init_cycfg_pins()
A Dcycfg_pins.h220 #define CYBSP_SWDCK_PIN 7U macro

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