1 /* 2 * Copyright (c) 2022 OpenLuat & AirM2M 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy of 5 * this software and associated documentation files (the "Software"), to deal in 6 * the Software without restriction, including without limitation the rights to 7 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 8 * the Software, and to permit persons to whom the Software is furnished to do so, 9 * subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in all 12 * copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 16 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 17 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 18 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 22 23 #ifndef AIRMCU_FLASH 24 #define AIRMCU_FLASH 25 26 #ifdef __cplusplus 27 extern "C" 28 { 29 #endif 30 31 #include <stdint.h> 32 #include "air105.h" 33 34 35 /* Size of the flash */ 36 #define X25Q_PAGE_SIZE 0x100 37 38 // Identification Operations 39 /***Command Definitions***/ 40 41 // Program Operations 42 #define PAGE_PROG_CMD 0x02 43 #define QUAD_INPUT_PAGE_PROG_CMD 0x32 44 45 46 // Erase Operations 47 #define SECTOR_ERASE_CMD 0x20 48 #define CHIP_ERASE_CMD 0xC7 49 50 #define PROG_ERASE_RESUME_CMD 0x7A 51 #define PROG_ERASE_SUSPEND_CMD 0x75 52 53 #define SET_BURST_WITH_WRAP 0x77 54 #define RELEASE_FROM_DEEP_POWER_DOWN 0xAB 55 #define DEEP_POWER_DOWN 0xB9 56 57 /***End Cmd***/ 58 59 60 #define QSPI_DEVICE_PARA_SAMPLE_DLY_Pos 15 61 #define QSPI_DEVICE_PARA_SAMPLE_PHA_Pos 14 62 #define QSPI_DEVICE_PARA_PROTOCOL_Pos 8 63 #define QSPI_DEVICE_PARA_DUMMY_CYCLE_Pos 4 64 65 66 #define ROM_QSPI_Init (*((void (*)(QSPI_InitTypeDef *))(*(uint32_t *)0x8010))) 67 #define ROM_QSPI_ReadID (*((uint32_t (*)(QSPI_CommandTypeDef *))(*(uint32_t *)0x8014))) 68 #define ROM_QSPI_WriteParam (*((uint8_t (*)(QSPI_CommandTypeDef *, uint16_t))(*(uint32_t *)0x8018))) 69 #define ROM_QSPI_EraseSector (*((uint8_t (*)(QSPI_CommandTypeDef *, uint32_t))(*(uint32_t *)0x801C))) 70 #define ROM_QSPI_ProgramPage (*((uint8_t (*)(QSPI_CommandTypeDef *, DMA_TypeDef *, uint32_t, uint32_t, uint8_t *))(*(uint32_t *)0x8024))) 71 #define ROM_QSPI_ReleaseDeepPowerDown (*((uint8_t (*)(QSPI_CommandTypeDef *))(*(uint32_t *)0x802C))) 72 #define ROM_QSPI_StatusReg (*((uint16_t (*)(QSPI_CommandTypeDef *))(*(uint32_t *)0x8034))) 73 74 75 typedef enum 76 { 77 QSPI_BUSMODE_111 = 0x00, //CMD-ADDR-DATA = 1-1-1 78 QSPI_BUSMODE_114 = 0x01, //CMD-ADDR-DATA = 1-1-4 79 QSPI_BUSMODE_144 = 0x02, //CMD-ADDR-DATA = 1-4-4 80 QSPI_BUSMODE_444 = 0x03, //CMD-ADDR-DATA = 4-4-4 81 }QSPI_BusModeTypeDef; 82 83 84 typedef enum 85 { 86 QSPI_CMDFORMAT_CMD8 = 0x00, 87 QSPI_CMDFORMAT_CMD8_RREG8 = 0x01, 88 QSPI_CMDFORMAT_CMD8_RREG16 = 0x02, 89 QSPI_CMDFORMAT_CMD8_RREG24 = 0x03, 90 QSPI_CMDFORMAT_CMD8_DMY24_WREG8 = 0x04, 91 QSPI_CMDFORMAT_CMD8_ADDR24_RREG8 = 0x05, 92 QSPI_CMDFORMAT_CMD8_ADDR24_RREG16 = 0x06, 93 QSPI_CMDFORMAT_CMD8_WREG8 = 0x07, 94 QSPI_CMDFORMAT_CMD8_WREG16 = 0x08, 95 QSPI_CMDFORMAT_CMD8_ADDR24 = 0x09, 96 QSPI_CMDFORMAT_CMD8_ADDR24_RDAT = 0x0A, 97 QSPI_CMDFORMAT_CMD8_ADDR24_DMY_RDAT = 0x0B, 98 QSPI_CMDFORMAT_CMD8_ADDR24_M8_DMY_RDAT = 0x0C, 99 QSPI_CMDFORMAT_CMD8_ADDR24_PDAT = 0x0D 100 }QSPI_CmdFormatTypeDef; 101 102 103 typedef enum 104 { 105 QSPI_PROTOCOL_CLPL = 0x00, 106 QSPI_PROTOCOL_CHPH = 0x03 107 }QSPI_ProtocolTypedef; 108 109 typedef enum 110 { 111 QSPI_FREQSEL_HCLK_DIV2 = 0x01, 112 QSPI_FREQSEL_HCLK_DIV3 = 0x02, 113 QSPI_FREQSEL_HCLK_DIV4 = 0x03 114 }QSPI_FreqSelTypeDef; 115 116 typedef struct 117 { 118 //Device Para 119 uint8_t SampleDly; //Default:0 120 uint8_t SamplePha; //Default:0 121 uint8_t ProToCol; //Defualt: QSPI_PROTOCOL_CLPL 122 uint8_t DummyCycles; //Include M7:0 Defualt: 6 123 uint8_t FreqSel; //Defualt: QSPI_FREQSEL_HCLK_DIV4 124 125 //Setting Cache 126 uint8_t Cache_Cmd_ReleaseDeepInstruction; //Defualt: 0xAB 127 uint8_t Cache_Cmd_DeepInstruction; //Defualt: 0xB9 128 uint8_t Cache_Cmd_ReadBusMode; //Defualt: QSPI_BUSMODE_144 129 uint8_t Cache_Cmd_ReadFormat; //Defualt: QSPI_CMDFORMAT_CMD8_ADDR24_DMY_RDAT 130 uint8_t Cache_Cmd_ReadInstruction; //Defualt: 0xEB 131 132 }QSPI_InitTypeDef; 133 134 typedef struct 135 { 136 uint8_t Instruction; 137 uint32_t BusMode; 138 uint32_t CmdFormat; 139 140 }QSPI_CommandTypeDef; 141 142 143 void QSPI_Init(QSPI_InitTypeDef *mhqspi); 144 void QSPI_SetLatency(uint32_t u32UsClk); 145 146 uint8_t FLASH_EraseSector(uint32_t sectorAddress); 147 uint8_t FLASH_ProgramPage(uint32_t addr, uint32_t size, uint8_t *buffer); 148 149 150 #ifdef __cplusplus 151 } 152 #endif 153 154 #endif 155 156