| /bsp/ft2004/libraries/bsp/standlone/ |
| A D | ft_cpu.c | 34 FCpu_Lock_t Clock; member
81 FCpu_Lock.Clock.Slock = 0; in FCpu_SpinLockInit()
93 "pld [%0]" ::"r"(&FCpu_Lock.Clock.Slock)); in FCpu_SpinLock()
102 : "r"(&FCpu_Lock.Clock.Slock), "I"(1 << 16) in FCpu_SpinLock()
109 LockVal.Tickets.owner = *(volatile unsigned short *)(&FCpu_Lock.Clock.Tickets.owner); in FCpu_SpinLock()
121 FCpu_Lock.Clock.Tickets.owner++; in FCpu_SpinUnlock()
|
| /bsp/microchip/same70/bsp/ |
| A D | atmel_start_config.atstart | 167 input: Master Clock (MCK)
171 afec_clock_source: Master Clock (MCK)
179 $input_id: Main Clock (MAINCK)
181 RESERVED_InputFreq_id: Main Clock (MAINCK)
186 _$freq_output_External Clock: 1
236 dummy_ext_clk_src: External Clock Input
275 mck_div_8_src: Master Clock (MCK)
290 pllack_ref_clock: Main Clock (MAINCK)
352 input: Master Clock (MCK)
404 input: Master Clock (MCK)
[all …]
|
| /bsp/ti/c28x/tms320f28379d/board/ |
| A D | Kconfig | 194 prompt "HSP Clock division"
197 bool "Clock Divided by 1"
199 bool "Clock Divided by 2"
201 bool "Clock Divided by 4"
209 prompt "Clock division"
212 bool "Clock Divided by 1"
214 bool "Clock Divided by 2"
414 prompt "HSP Clock division"
429 prompt "Clock division"
649 prompt "Clock division"
[all …]
|
| /bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ |
| A D | ht32f1xxxx_ckcu.c | 636 CKCU_ClocksTypeDef Clock; in CKCU_GetPeripFrequency() local
639 CKCU_GetClocksFrequency(&Clock); in CKCU_GetPeripFrequency()
640 return Clock.HCLK_Freq; in CKCU_GetPeripFrequency()
653 CKCU_GetClocksFrequency(&Clock); in CKCU_GetPeripFrequency()
654 return (Clock.HCLK_Freq >> (PCLKPrescaler)); in CKCU_GetPeripFrequency()
936 uAHBCCR &= ~(Clock.Reg[0]); in CKCU_PeripClockConfig()
937 uAPBCCR0 &= ~(Clock.Reg[1]); in CKCU_PeripClockConfig()
938 uAPBCCR1 &= ~(Clock.Reg[2]); in CKCU_PeripClockConfig()
942 uAHBCCR |= Clock.Reg[0]; in CKCU_PeripClockConfig()
943 uAPBCCR0 |= Clock.Reg[1]; in CKCU_PeripClockConfig()
[all …]
|
| /bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ |
| A D | ht32f5xxxx_ckcu.c | 706 CKCU_ClocksTypeDef Clock; in CKCU_GetPeripFrequency() local
720 CKCU_GetClocksFrequency(&Clock); in CKCU_GetPeripFrequency()
721 return (Clock.HCLK_Freq >> (PCLKPrescaler)); in CKCU_GetPeripFrequency()
973 void CKCU_PeripClockConfig(CKCU_PeripClockConfig_TypeDef Clock, ControlStatus Cmd) in CKCU_PeripClockConfig() argument
983 uAHBCCR &= ~(Clock.Reg[0]); in CKCU_PeripClockConfig()
984 uAPBCCR0 &= ~(Clock.Reg[1]); in CKCU_PeripClockConfig()
985 uAPBCCR1 &= ~(Clock.Reg[2]); in CKCU_PeripClockConfig()
989 uAHBCCR |= Clock.Reg[0]; in CKCU_PeripClockConfig()
990 uAPBCCR0 |= Clock.Reg[1]; in CKCU_PeripClockConfig()
991 uAPBCCR1 |= Clock.Reg[2]; in CKCU_PeripClockConfig()
|
| /bsp/stm32/stm32mp157a-st-discovery/board/ports/ |
| A D | drv_lptim.c | 97 hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; in lptim_init()
98 hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV8; in lptim_init()
|
| /bsp/stm32/stm32mp157a-st-ev1/board/ports/ |
| A D | drv_lptim.c | 99 hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; in lptim_init()
100 hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV8; in lptim_init()
|
| /bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/ |
| A D | README.md | 27 ### Clock Configuration
29 | Clock | Source | Output Frequency |
|
| /bsp/microchip/samd51-adafruit-metro-m4/bsp/hal/documentation/ |
| A D | usb_device_async.rst | 131 * USB Clock Recovery Mode
134 "USB Clock Recovery Mode", "Stable DFLL Frequency"
141 * Clear "USB Clock Recovery Mode", "Stable DFLL Frequency"
144 * Select "Reference Clock Source" to use 32768Hz source, e.g., use GCLK1 and
147 * Set "Generic Clock Generator Enable"
|
| /bsp/microchip/samd51-seeed-wio-terminal/bsp/hal/documentation/ |
| A D | usb_device_async.rst | 131 * USB Clock Recovery Mode
134 "USB Clock Recovery Mode", "Stable DFLL Frequency"
141 * Clear "USB Clock Recovery Mode", "Stable DFLL Frequency"
144 * Select "Reference Clock Source" to use 32768Hz source, e.g., use GCLK1 and
147 * Set "Generic Clock Generator Enable"
|
| /bsp/stm32/docs/ |
| A D | STM32系列外设驱动添加指南.md | 94 | 5 | TIMER | **使能 internal Clock 时钟** ，详细内容可参考5.3章节 |
95 | 7 | PWM | **首先使能 internal Clock 时钟，然后为 channelx 选项选择PWM Generation CHx，** 最后配置所需要的引脚（或者使用…
|
| /bsp/nxp/imx/imx6ull-smart/ |
| A D | Kconfig | 33 int "Disable Clock control in fsl files"
|
| /bsp/at91/at91sam9260/debug_scripts/ |
| A D | at91sam9260.gdb | 50 # AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) #(PMC) Peripheral Clock Disable Register
54 # AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) # (PMC) Master Clock Register
94 # AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) # (PMC) Master Clock Register
|
| A D | at91sam9260.ini | 91 // AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
95 // AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
130 // AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
|
| A D | at91sam9260.mac | 200 //* AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
205 // AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
237 // AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
|
| /bsp/stm32/libraries/HAL_Drivers/drivers/ |
| A D | drv_lptim.c | 99 tim->Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; in timer_init()
100 tim->Init.Clock.Prescaler = LPTIM_PRESCALER_DIV32; in timer_init()
|
| /bsp/loongson/ls1bdev/ |
| A D | Kconfig | 23 int "Oscillator Clock (Hz)"
|
| /bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/ |
| A D | README.md | 38 ### Clock Configuration
40 | Clock | Source | Output Frequency |
|
| /bsp/microchip/samc21/bsp/hal/documentation/ |
| A D | i2c_master_sync.rst | 11 designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
77 Clock considerations
|
| /bsp/microchip/saml10/bsp/hal/documentation/ |
| A D | i2c_master_sync.rst | 11 designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
77 Clock considerations
|
| /bsp/microchip/same70/bsp/hal/documentation/ |
| A D | i2c_master_sync.rst | 11 designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
77 Clock considerations
|
| /bsp/microchip/same54/bsp/hal/documentation/ |
| A D | i2c_master_sync.rst | 11 designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
77 Clock considerations
|
| /bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/ |
| A D | n32l43x_usart.c | 287 assert_param(IS_USART_CLOCK(USART_ClockInitStruct->Clock)); in USART_ClockInit()
301 tmpregister |= (uint32_t)USART_ClockInitStruct->Clock | USART_ClockInitStruct->Polarity in USART_ClockInit()
315 USART_ClockInitStruct->Clock = USART_CLK_DISABLE; in USART_ClockStructInit()
|
| /bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/ |
| A D | n32l40x_usart.c | 287 assert_param(IS_USART_CLOCK(USART_ClockInitStruct->Clock)); in USART_ClockInit()
301 tmpregister |= (uint32_t)USART_ClockInitStruct->Clock | USART_ClockInitStruct->Polarity in USART_ClockInit()
315 USART_ClockInitStruct->Clock = USART_CLK_DISABLE; in USART_ClockStructInit()
|
| /bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/ |
| A D | n32g43x_usart.c | 287 assert_param(IS_USART_CLOCK(USART_ClockInitStruct->Clock)); in USART_ClockInit()
301 tmpregister |= (uint32_t)USART_ClockInitStruct->Clock | USART_ClockInitStruct->Polarity in USART_ClockInit()
315 USART_ClockInitStruct->Clock = USART_CLK_DISABLE; in USART_ClockStructInit()
|