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Searched refs:Config (Results 1 – 25 of 809) sorted by relevance

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/bsp/ft2004/libraries/bsp/ft_gmac/
A Dft_gmac_hw.c37 TmpReg |= GMAC_MII_ADDR_CR(Config->clkMDC); in Gmac_WritePHYRegister()
64 TmpReg |= GMAC_MII_ADDR_CR(Config->clkMDC); in FGmac_ReadPHYRegister()
95 static s32 FGmac_PhyAddrGet(FGmac_Config_t *Config) in FGmac_PhyAddrGet() argument
104 Config->PhyAddr = i; in FGmac_PhyAddrGet()
136 static void FGmac_MACDMAInit(FGmac_Config_t *Config) in FGmac_MACDMAInit() argument
161 if (Config->ChecksumMode) in FGmac_MACDMAInit()
174 if (Config->DuplexMode == GMAC_MODE_FULLDUPLEX) in FGmac_MACDMAInit()
276 FGmac_MACAddressConfig(Config, 0, Config->MacAddr); in FGmac_MACDMAInit()
279 s32 FGmac_InitializeHw(FGmac_Config_t *Config) in FGmac_InitializeHw() argument
300 …Ft_out32(Config->BaseAddress + DMA_OP_OFFSET, Ft_in32(Config->BaseAddress + DMA_OP_OFFSET) | DMA_O… in FGmac_InitializeHw()
[all …]
A Dft_gmac.c43 Ft_assertNonvoid(Config != NULL); in Ft_GmacCfgInitialize()
45 Gmac->Config = *Config; in Ft_GmacCfgInitialize()
57 FGmac_Config_t *Config = NULL; in Ft_Gmac_Start() local
60 Config = &Gmac->Config; in Ft_Gmac_Start()
73 FGmac_Config_t *Config = NULL; in Ft_Gmac_Stop() local
76 Config = &Gmac->Config; in Ft_Gmac_Stop()
78 FGmac_TransmissionDisable(Config); in Ft_Gmac_Stop()
79 FGmac_ReceptionDisable(Config); in Ft_Gmac_Stop()
80 FGmac_DMATransmissionDisable(Config); in Ft_Gmac_Stop()
81 FGmac_DMAReceptionDisable(Config); in Ft_Gmac_Stop()
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A Dft_gmac_intr.c67 RegValue = Ft_in32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET); in FGmac_ErrorCheck()
68 ErrIsr_RegValue = Ft_in32(Gmac->Config.BaseAddress + DMA_INTR_ENA_OFFSET); in FGmac_ErrorCheck()
137 RegValue = Ft_in32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET); in FGmac_IntrHandler()
140 MACRegValue = Ft_in32(Gmac->Config.BaseAddress + GMAC_MAC_MAC_PHY_STATUS); in FGmac_IntrHandler()
155 Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_RI); in FGmac_IntrHandler()
160 …Ft_printf("ti debug %x \r\n", Ft_in32(Gmac->Config.BaseAddress + GMAC_INTERNAL_MODULE_STATUS_OFFSE… in FGmac_IntrHandler()
162 Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_TI); in FGmac_IntrHandler()
165 Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_NIS); in FGmac_IntrHandler()
168 if ((Ft_in32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET) & DMA_STATUS_AIS) == DMA_STATUS_AIS) in FGmac_IntrHandler()
172 …Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, Ft_in32(Gmac->Config.BaseAddress + DMA_STAT… in FGmac_IntrHandler()
A Dft_gmac_hw.h471 s32 FGmac_InitializeHw(FGmac_Config_t *Config);
499 void FGmac_TransmissionEnable(FGmac_Config_t *Config);
507 void FGmac_TransmissionDisable(FGmac_Config_t *Config);
515 void FGmac_ReceptionEnable(FGmac_Config_t *Config);
523 void FGmac_ReceptionDisable(FGmac_Config_t *Config);
539 void FGmac_ReceptionTransmissionEnable(FGmac_Config_t *Config);
547 void FGmac_FlushTransmitFIFO(FGmac_Config_t *Config);
555 void FGmac_DMATransmissionEnable(FGmac_Config_t *Config);
562 void FGmac_DMATransmissionDisable(FGmac_Config_t *Config);
569 void FGmac_DMAReceptionEnable(FGmac_Config_t *Config);
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A Dft_gmac_desc.c35 if ((Ft_in32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET) & DMA_STATUS_TU) == DMA_STATUS_TU) in FGmac_ResumeTransmission()
38 Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_TU); in FGmac_ResumeTransmission()
41 Ft_out32(Gmac->Config.BaseAddress + DMA_XMT_POLL_DEMAND_OFFSET, 0xff); in FGmac_ResumeTransmission()
48 if ((Ft_in32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET) & DMA_STATUS_UNF) == DMA_STATUS_UNF) in FGmac_SetTransmitUnderflow()
51 Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_UNF); in FGmac_SetTransmitUnderflow()
54 Ft_out32(Gmac->Config.BaseAddress + DMA_XMT_POLL_DEMAND_OFFSET, 0xff); in FGmac_SetTransmitUnderflow()
108 Ft_out32(Gmac->Config.BaseAddress + DMA_TX_BASE_ADDR_OFFSET, (u32)DMATxDescTab); in FGmac_DmaTxDescRingInit()
223 Ft_out32(Gmac->Config.BaseAddress + DMA_RCV_BASE_ADDR_OFFSET, (u32)DMARxDescTab); in FGmac_DMARxDescChainInit()
255 Ft_out32(Gmac->Config.BaseAddress + DMA_RCV_BASE_ADDR_OFFSET, (u32)DMARxDescTab); in FGmac_DmaRxDescRingInit()
266 Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_RU); in FGmac_ResumeTransmissionReception()
[all …]
/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/
A Dxemacps.c88 InstancePtr->Config.DeviceId = CfgPtr->DeviceId; in XEmacPs_CfgInitialize()
89 InstancePtr->Config.BaseAddress = EffectiveAddress; in XEmacPs_CfgInitialize()
92 InstancePtr->Config.RefClk = CfgPtr->RefClk; in XEmacPs_CfgInitialize()
145 Xil_ClockEnable(InstancePtr->Config.RefClk); in XEmacPs_Start()
156 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_Start()
160 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_Start()
248 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_Stop()
254 Xil_ClockDisable(InstancePtr->Config.RefClk); in XEmacPs_Stop()
316 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_Reset()
330 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_Reset()
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A Dxemacps_control.c89 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_SetMacAddress()
102 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_SetMacAddress()
244 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_SetHash()
250 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_SetHash()
338 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_ClearHash()
342 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_ClearHash()
404 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_SetTypeIdCheck()
795 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_SendPausePacket()
928 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_SetMdioDivisor()
993 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_PhyRead()
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A Dxemacps_intr.c138 RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
155 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
167 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
170 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
181 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
191 RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
193 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
201 XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
204 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
223 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
[all …]
A Dxemacps.h526 XEmacPs_Config Config; /* Hardware configuration */ member
601 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
622 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
643 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
664 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
683 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
685 (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
707 ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
730 ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
757 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
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/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/
A Dtae32f53xx_ll_iir.c176 assert_param(IS_IIR_INPUT_DATA_SCALE(Config->InDataScale)); in LL_IIR_FilterConfig()
177 assert_param(IS_IIR_OUTPUT_DATA_SCALE(Config->OutDataScale)); in LL_IIR_FilterConfig()
178 assert_param(IS_IIR_FEEDBACK_SCALE(Config->FeedBackScale)); in LL_IIR_FilterConfig()
186 WRITE_REG(Instance->DIAR, Config->InDataAddress); in LL_IIR_FilterConfig()
189 for (int idx = 0; idx < ARRAY_SIZE(Config->AxCOEF); idx++) { in LL_IIR_FilterConfig()
193 for (int idx = 0; idx < ARRAY_SIZE(Config->BxCOEF); idx++) { in LL_IIR_FilterConfig()
215 assert_param(IS_IIR_INPUT_DATA_SCALE(Config->InDataScale)); in LL_IIR_FilterConfig_Preload()
216 assert_param(IS_IIR_OUTPUT_DATA_SCALE(Config->OutDataScale)); in LL_IIR_FilterConfig_Preload()
217 assert_param(IS_IIR_FEEDBACK_SCALE(Config->FeedBackScale)); in LL_IIR_FilterConfig_Preload()
225 WRITE_REG(Instance->DIASR, Config->InDataAddress); in LL_IIR_FilterConfig_Preload()
[all …]
A Dtae32f53xx_ll_tmr.c217 assert_param(Config != NULL); in LL_TMR_TB_Config()
220 TMR_TB_SetConfig(Instance, Config); in LL_TMR_TB_Config()
240 assert_param(Config != NULL); in LL_TMR_IC_Config()
246 TMR_IC_SetConfig(Instance, Config); in LL_TMR_IC_Config()
265 assert_param(Config != NULL); in LL_TMR_OC_Config()
271 TMR_OC_SetConfig(Instance, Config); in LL_TMR_OC_Config()
291 assert_param(Config != NULL); in LL_TMR_EXT_Config()
294 TMR_EXT_SetConfig(Instance, Config); in LL_TMR_EXT_Config()
689 WRITE_REG(Instance->CEVR, Config->EndValue); in TMR_TB_SetConfig()
696 …WRITE_REG(Instance->CR, (Config->ClockSource | Config->AutoReloadPreload | Config->ContinuousMode | in TMR_TB_SetConfig()
[all …]
/bsp/ft2004/libraries/bsp/ft_uart/
A Dft_uart.c35 s32 FUart_CfgInitialize(Ft_Uart *UartPtr, FUart_Config_t *Config) in FUart_CfgInitialize() argument
40 Ft_assertNonvoid(Config != NULL); in FUart_CfgInitialize()
42 UartPtr->Config.InstanceId = Config->InstanceId; in FUart_CfgInitialize()
43 UartPtr->Config.BaseAddress = Config->BaseAddress; in FUart_CfgInitialize()
44 UartPtr->Config.RefClockHz = Config->RefClockHz; in FUart_CfgInitialize()
45 UartPtr->Config.IsrNum = Config->IsrNum; in FUart_CfgInitialize()
125 while (!FT_UART_IsTransmitFull(UartPtr->Config.BaseAddress)) in FUart_PutChar()
287 return FUart_RecvByte(UartPtr->Config.BaseAddress); in FUart_BlockReceive()
305 if ((BaudRate * 2) > UartPtr->Config.RefClockHz) in FUart_SetBaudRate()
312 divider = UartPtr->Config.RefClockHz / temp; in FUart_SetBaudRate()
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A Dft_uart_options.c47 RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset); in FUart_SetOptions()
58 FT_UART_WriteReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset, RegValue); in FUart_SetOptions()
75 RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset); in FUart_SetSpecificOptions()
79 FT_UART_WriteReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset, RegValue); in FUart_SetSpecificOptions()
96 RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset); in FUart_ClearSpecificOptions()
100 FT_UART_WriteReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset, RegValue); in FUart_ClearSpecificOptions()
A Dft_uart_intr.c35 return FT_UART_ReadReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET); in FUart_GetInterruptMask()
45 FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET, TempMask); in FUart_SetInterruptMask()
77 RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET); in FUart_InterruptHandler()
79 RegValue &= FT_UART_ReadReg(UartPtr->Config.BaseAddress, UARTMIS_OFFSET); in FUart_InterruptHandler()
111 FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTICR_OFFSET, in FUart_InterruptHandler()
181 RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET); in FUart_sendDataHandler()
183 FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET, RegValue); in FUart_sendDataHandler()
/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/
A Dxsdps.c140 InstancePtr->Config.RefClk = ConfigPtr->RefClk; in XSdPs_CfgInitialize()
141 Xil_ClockEnable(InstancePtr->Config.RefClk); in XSdPs_CfgInitialize()
192 Xil_ClockDisable(InstancePtr->Config.RefClk); in XSdPs_CfgInitialize()
231 Xil_ClockEnable(InstancePtr->Config.RefClk); in XSdPs_CardInitialize()
265 Xil_ClockDisable(InstancePtr->Config.RefClk); in XSdPs_CardInitialize()
295 Xil_ClockEnable(InstancePtr->Config.RefClk); in XSdPs_ReadPolled()
314 Xil_ClockDisable(InstancePtr->Config.RefClk); in XSdPs_ReadPolled()
344 Xil_ClockEnable(InstancePtr->Config.RefClk); in XSdPs_WritePolled()
363 Xil_ClockDisable(InstancePtr->Config.RefClk); in XSdPs_WritePolled()
390 Xil_ClockEnable(InstancePtr->Config.RefClk); in XSdPs_Idle()
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A Dxsdps_card.c87 if (InstancePtr->Config.IsCacheCoherent == 0U) { in XSdPs_Read()
192 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_IdentifyCard()
194 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_IdentifyCard()
240 InstancePtr->Config.BusWidth = XSDPS_WIDTH_4; in XSdPs_SdCardInitialize()
352 if(InstancePtr->Config.CardDetect != 0U) { in XSdPs_CheckCardDetect()
743 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_HostConfig()
886 if (InstancePtr->Config.BankNumber == 2U) { in XSdPs_Identify_UhsMode()
1203 if (InstancePtr->Config.IsCacheCoherent == 0U) { in XSdPs_SetupADMA2DescTbl64Bit()
1236 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_DllReset()
1439 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, in XSdPs_SetupCmd()
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A Dxsdps_host.c106 if(InstancePtr->Config.CardDetect != 0U) { in XSdPs_SetupTransfer()
118 if(XSdPs_ReadReg(InstancePtr->Config.BaseAddress, in XSdPs_SetupTransfer()
183 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_SetExecTuning()
725 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_EnableClock()
744 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_EnableClock()
844 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_SetupReadDma()
972 if (InstancePtr->Config.IsCacheCoherent == 0U) { in XSdPs_Setup32ADMA2DescTbl()
1045 if (InstancePtr->Config.IsCacheCoherent == 0U) { in XSdPs_Setup64ADMA2DescTbl()
1112 DeviceId = InstancePtr->Config.DeviceId; in XSdPs_DllRstCtrl()
1208 DeviceId = InstancePtr->Config.DeviceId ; in XSdPs_ConfigTapDelay()
[all …]
A Dxsdps_options.c209 if (InstancePtr->Config.IsCacheCoherent == 0U) { in XSdPs_Get_BusWidth()
251 (InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) { in XSdPs_Change_BusWidth()
294 StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, in XSdPs_Change_BusWidth()
304 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, in XSdPs_Change_BusWidth()
309 StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, in XSdPs_Change_BusWidth()
313 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_Change_BusWidth()
376 if (InstancePtr->Config.IsCacheCoherent == 0U) { in XSdPs_Get_BusSpeed()
439 if (InstancePtr->Config.IsCacheCoherent == 0U) { in XSdPs_Get_Status()
506 StatusReg = (u32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, in XSdPs_Change_BusSpeed()
509 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, in XSdPs_Change_BusSpeed()
[all …]
/bsp/ft2004/libraries/bsp/ft_i2c/
A Dft_i2c.c174 FI2C_resetReg(pDev->Config.BaseAddress); in FI2C_initMaster()
178 pDev->Config.BusSpeed, in FI2C_initMaster()
179 pDev->Config.SclLcnt, in FI2C_initMaster()
180 pDev->Config.SclHcnt); in FI2C_initMaster()
278 if (pDev->Config.BlockSize <= len) in FI2C_writeByByte()
292 if (!pDev->Config.IsPolling) in FI2C_writeByByte()
300 if (pDev->Config.IsPolling) in FI2C_writeByByte()
363 if (!pDev->Config.IsPolling) in FI2C_readByByte()
372 if (pDev->Config.IsPolling) in FI2C_readByByte()
423 if (pDev->Config.IsPolling) in FI2C_writeByFifo()
[all …]
/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/
A Dxemacpsif_dma.c147 if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) { in get_base_index_txpbufsstorage()
152 if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_1_BASEADDR) { in get_base_index_txpbufsstorage()
157 if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_2_BASEADDR) { in get_base_index_txpbufsstorage()
315 if (xemacpsif->emacps.Config.IsCacheCoherent == 0) { in emacps_sgsend()
362 XEmacPs_WriteReg((xemacpsif->emacps).Config.BaseAddress, in emacps_sgsend()
364 (XEmacPs_ReadReg((xemacpsif->emacps).Config.BaseAddress, in emacps_sgsend()
420 if (xemacpsif->emacps.Config.IsCacheCoherent == 0) { in setup_rx_bds()
424 if (xemacpsif->emacps.Config.IsCacheCoherent == 0) { in setup_rx_bds()
704 if (xemacpsif->emacps.Config.IsCacheCoherent == 0) { in init_dma()
708 if (xemacpsif->emacps.Config.IsCacheCoherent == 0) { in init_dma()
[all …]
A Dxemacpsif_hw.c112 if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) { in init_emacps()
127 if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) { in init_emacps()
203 Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress, in restart_emacps_transmitter()
206 XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress, in restart_emacps_transmitter()
209 Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress, in restart_emacps_transmitter()
212 XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress, in restart_emacps_transmitter()
/bsp/ft2004/drivers/
A Ddrv_usart.c40 …RT_ASSERT(FUart_CfgInitialize(uart_ptr, FUart_LookupConfig(uart_ptr->Config.InstanceId)) == FST_SU… in uart_configure()
42 rt_hw_interrupt_install(uart_ptr->Config.IsrNum, rt_hw_uart_isr, uart_ptr, "uart"); in uart_configure()
43 rt_hw_interrupt_umask(uart_ptr->Config.IsrNum); in uart_configure()
70 rt_hw_interrupt_mask(uart_ptr->Config.IsrNum); in uart_control()
75 rt_hw_interrupt_umask(uart_ptr->Config.IsrNum); in uart_control()
121 FUart_SendByte(uart_ptr->Config.BaseAddress, c); in uart_putc()
136 ch = FUart_GetChar(uart_ptr->Config.BaseAddress); in uart_getc()
170 Ft_Uart0.Config.InstanceId = FT_UART0_ID; in rt_hw_uart_init()
182 Ft_Uart1.Config.InstanceId = FT_UART1_ID; in rt_hw_uart_init()
A Ddrv_can.c30 .can_handle.Config.InstanceId = 0};
37 .can_handle.Config.InstanceId = 1};
60 …FCan_CfgInitialize(&drv_can->can_handle, FCan_LookupConfig(drv_can->can_handle.Config.InstanceId)); in _can_config()
74 rt_hw_interrupt_set_priority(drv_can->can_handle.Config.IrqNum, 16); in _can_config()
75 …rt_hw_interrupt_install(drv_can->can_handle.Config.IrqNum, rt_hw_inner_can_isr, &drv_can->can_hand… in _can_config()
76 rt_hw_interrupt_umask(drv_can->can_handle.Config.IrqNum); in _can_config()
178 drv_can0.can_handle.Config.InstanceId = 0; in rt_hw_can_init()
190 drv_can1.can_handle.Config.InstanceId = 1; in rt_hw_can_init()
/bsp/stm32/libraries/HAL_Drivers/drivers/
A Ddrv_nand.c54 hnand1.Config.PageSize = NAND_PAGE_SIZE; in rt_nand_init()
55 hnand1.Config.SpareAreaSize = 64; in rt_nand_init()
56 hnand1.Config.BlockSize = 64; in rt_nand_init()
57 hnand1.Config.BlockNbr = 1024; in rt_nand_init()
58 hnand1.Config.PlaneNbr = 1; in rt_nand_init()
59 hnand1.Config.PlaneSize = 1024; in rt_nand_init()
60 hnand1.Config.ExtraCommandEnable = DISABLE; in rt_nand_init()
/bsp/ft2004/libraries/bsp/ft_spi/
A Dft_spi.c88 if (SPI_CTRL_CPHA_1EDGE == pCtrl->Config.Cpha) in FSpi_Init()
92 else if (SPI_CTRL_CPHA_2EDGE == pCtrl->Config.Cpha) in FSpi_Init()
101 if (SPI_CTRL_CPOL_LOW == pCtrl->Config.Cpol) in FSpi_Init()
105 else if (SPI_CTRL_CPOL_HIGH == pCtrl->Config.Cpol) in FSpi_Init()
120 FSPI_SET_BAUDR(pCtrl, pCtrl->Config.BaudRDiv); in FSpi_Init()

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