| /bsp/ft2004/libraries/bsp/ft_gmac/ |
| A D | ft_gmac_desc.c | 69 TxDesc->Control = DMA_TDES1_SECOND_ADDRESS_CHAINED; in FGmac_DMATxDescChainInit()
101 DMATxDescTab[TxBuffCount - 1].Control |= DMA_TDES1_END_RING; in FGmac_DmaTxDescRingInit()
145 TxDesc->Control &= ~(DMA_TDES1_BUFFER1_SIZE_MASK); in FGmac_TransmitframeRingPoll()
146 TxDesc->Control |= (FrameLength & DMA_TDES1_BUFFER1_SIZE_MASK); in FGmac_TransmitframeRingPoll()
162 TxDesc->Control |= DMA_TDES1_FIRST_SEGMENT; in FGmac_TransmitframeRingPoll()
166 TxDesc->Control &= ~(DMA_TDES1_BUFFER1_SIZE_MASK); in FGmac_TransmitframeRingPoll()
172 TxDesc->Control |= (DMA_TDES1_LAST_SEGMENT); in FGmac_TransmitframeRingPoll()
174 TxDesc->Control &= ~(DMA_TDES1_BUFFER1_SIZE_MASK); in FGmac_TransmitframeRingPoll()
175 TxDesc->Control |= (Size & DMA_TDES1_BUFFER1_SIZE_MASK); in FGmac_TransmitframeRingPoll()
205 RxDesc->Control |= DMA_RDES1_SECOND_ADDRESS_CHAINED; in FGmac_DMARxDescChainInit()
[all …]
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| A D | ft_gmac.h | 100 u32 Control; /*!< Control and Buffer1, Buffer2 lengths */ member
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| /bsp/microchip/samc21/bsp/samc21/armcc/Device/SAMC21/Source/ARM/ |
| A D | startup_SAMC21.s | 81 … SYSTEM_Handler ; 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peri…
96 DCD CAN0_Handler ; 15 Control Area Network 0
97 DCD CAN1_Handler ; 16 Control Area Network 1
98 DCD TCC0_Handler ; 17 Timer Counter Control 0
99 DCD TCC1_Handler ; 18 Timer Counter Control 1
100 DCD TCC2_Handler ; 19 Timer Counter Control 2
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| /bsp/ti/c28x/libraries/tms320f28379d/common/source/ |
| A D | F2837xD_can.c | 78 CanaRegs.CAN_IF1CMD.bit.Control = 1; in InitCAN()
86 CanaRegs.CAN_IF2CMD.bit.Control = 1; in InitCAN()
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| /bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ |
| A D | ht32f1xxxx_mctm.c | 100 void MCTM_ChannelNConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control) in MCTM_ChannelNConfig() argument
105 Assert_Param(IS_TM_CHCTL(Control)); in MCTM_ChannelNConfig()
111 MCTMx->CHCTR |= (u32)(Control << 1) << (Channel << 1); in MCTM_ChannelNConfig()
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| A D | ht32f1xxxx_tm.c | 220 Assert_Param(IS_TM_CHCTL(OutInit->Control)); in TM_OutputInit()
272 TMx->CHCTR |= (u32)(OutInit->Control | (OutInit->ControlN << 1)) << bChPos; in TM_OutputInit()
276 TMx->CHCTR |= (u32)(OutInit->Control) << bChPos; in TM_OutputInit()
391 OutInit->Control = TM_CHCTL_DISABLE; in TM_OutputStructInit()
910 void TM_ChannelConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control) in TM_ChannelConfig() argument
915 Assert_Param(IS_TM_CHCTL(Control)); in TM_ChannelConfig()
921 TMx->CHCTR |= (u32)Control << (Channel << 1); in TM_ChannelConfig()
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| A D | ht32_serial.c | 210 …#error USB Endpoint of retarget Control and Tx must different. Please check RETARGET_CTRL_EPT/RETA…
214 …#error USB Endpoint of retarget Control and Rx must different. Please check RETARGET_CTRL_EPT/RETA…
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| /bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ |
| A D | ht32f5xxxx_mctm.c | 100 void MCTM_ChannelNConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control) in MCTM_ChannelNConfig() argument
105 Assert_Param(IS_TM_CHCTL(Control)); in MCTM_ChannelNConfig()
111 MCTMx->CHCTR |= (u32)(Control << 1) << (Channel << 1); in MCTM_ChannelNConfig()
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| A D | ht32f5xxxx_tm.c | 260 Assert_Param(IS_TM_CHCTL(OutInit->Control)); in TM_OutputInit()
314 TMx->CHCTR |= (u32)(OutInit->Control | (OutInit->ControlN << 1)) << bChPos; in TM_OutputInit()
319 TMx->CHCTR |= (u32)(OutInit->Control) << bChPos; in TM_OutputInit()
459 OutInit->Control = TM_CHCTL_DISABLE; in TM_OutputStructInit()
1034 void TM_ChannelConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control) in TM_ChannelConfig() argument
1039 Assert_Param(IS_TM_CHCTL(Control)); in TM_ChannelConfig()
1045 TMx->CHCTR |= (u32)Control << (Channel << 1); in TM_ChannelConfig()
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| A D | ht32_serial.c | 205 …#error USB Endpoint of retarget Control and Tx must different. Please check RETARGET_CTRL_EPT/RETA…
209 …#error USB Endpoint of retarget Control and Rx must different. Please check RETARGET_CTRL_EPT/RETA…
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| /bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/arm/ |
| A D | startup_SAMD21.s | 82 DCD SYSCTRL_Handler ; 1 System Control
96 DCD TCC0_Handler ; 15 Timer Counter Control 0
97 DCD TCC1_Handler ; 16 Timer Counter Control 1
98 DCD TCC2_Handler ; 17 Timer Counter Control 2
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| /bsp/microchip/same70/bsp/documentation/ |
| A D | ethernet_phy.rst | 22 The MII basic register set consists of two registers referred to as the Control
26 Control register (Register 0), Status register (Register 1), and Extended
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| /bsp/microchip/same54/bsp/documentation/ |
| A D | ethernet_phy.rst | 22 The MII basic register set consists of two registers referred to as the Control
26 Control register (Register 0), Status register (Register 1), and Extended
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| /bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ |
| A D | ht32f1xxxx_mctm.h | 212 void MCTM_ChannelNConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control);
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| /bsp/phytium/aarch32/ |
| A D | rtconfig.h.origin | 465 /* Signal Processing and Control Algorithm Packages */
467 /* end of Signal Processing and Control Algorithm Packages */
513 /* Device Control */
515 /* end of Device Control */
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| /bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Src/ |
| A D | HAL_DMA.c | 256 Cycle_Channel[lu32_Channel_Index].Control = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; in HAL_DMA_CycleMode_Start()
301 Cycle_Channel[lu32_Channel_Index].Control = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; in HAL_DMA_CycleMode_Start_IT()
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| /bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/ |
| A D | HAL_DMA.c | 254 Cycle_Channel[lu32_Channel_Index].Control = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; in HAL_DMA_CycleMode_Start()
299 Cycle_Channel[lu32_Channel_Index].Control = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; in HAL_DMA_CycleMode_Start_IT()
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| /bsp/rm48x50/HALCoGen/include/ |
| A D | het.h | 277 uint32 Control; member
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| /bsp/nxp/lpc/lpc408x/drivers/ |
| A D | drv_sdram.c | 90 LPC_EMC->Control = 0x00000001; in rt_hw_sdram_init()
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| /bsp/microchip/samd51-seeed-wio-terminal/bsp/documentation/ |
| A D | usb_device_cdc.rst | 6 It provides support for Abstract Control Model, which is one of the USB PSTN Device
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| /bsp/microchip/samd51-adafruit-metro-m4/bsp/documentation/ |
| A D | usb_device_cdc.rst | 6 It provides support for Abstract Control Model, which is one of the USB PSTN Device
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| /bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ |
| A D | ht32f5xxxx_mctm.h | 269 void MCTM_ChannelNConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control);
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| /bsp/microchip/same54/ |
| A D | README_zh.md | 65 - Two 24-bit Timer/Counters for Control (TCC), with extended functions
66 - Up to Three 16-bit Timer/Counters for Control (TCC) with extended functions.
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| /bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/ |
| A D | HAL_DMA.h | 186 uint32_t Control; /* Control */ member
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| /bsp/microchip/samd51-adafruit-metro-m4/ |
| A D | README_zh.md | 71 - Two 24-bit Timer/Counters for Control (TCC), with extended functions
72 - Up to Three 16-bit Timer/Counters for Control (TCC) with extended functions.
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