| /bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ |
| A D | ft32f0xx_wwdg.c | 100 void WWDG_SetCounter(uint8_t Counter) in WWDG_SetCounter() argument
103 assert_param(IS_WWDG_COUNTER(Counter)); in WWDG_SetCounter()
106 WWDG->CR = Counter & BIT_MASK; in WWDG_SetCounter()
120 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
123 assert_param(IS_WWDG_COUNTER(Counter)); in WWDG_Enable()
124 WWDG->CR = WWDG_CR_WDGA | Counter; in WWDG_Enable()
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| /bsp/tkm32F499/Libraries/Hal_lib/src/ |
| A D | HAL_wwdg.c | 170 void WWDG_SetCounter(uint8_t Counter)
173 assert_param(IS_WWDG_COUNTER(Counter));
176 WWDG->CR = Counter & BIT_Mask;
185 void WWDG_Enable(uint8_t Counter)
188 assert_param(IS_WWDG_COUNTER(Counter));
189 WWDG->CR = CR_WDGA_Set | Counter;
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| /bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/src/ |
| A D | HAL_wwdg.c | 167 void WWDG_SetCounter(uint8_t Counter) in WWDG_SetCounter() argument
170 assert_param(IS_WWDG_COUNTER(Counter)); in WWDG_SetCounter()
173 WWDG->CR = Counter & BIT_Mask; in WWDG_SetCounter()
182 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
185 assert_param(IS_WWDG_COUNTER(Counter)); in WWDG_Enable()
186 WWDG->CR = CR_WDGA_Set | Counter; in WWDG_Enable()
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| /bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/src/ |
| A D | HAL_wwdg.c | 167 void WWDG_SetCounter(uint8_t Counter) in WWDG_SetCounter() argument
170 assert_param(IS_WWDG_COUNTER(Counter)); in WWDG_SetCounter()
173 WWDG->CR = Counter & BIT_Mask; in WWDG_SetCounter()
182 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
185 assert_param(IS_WWDG_COUNTER(Counter)); in WWDG_Enable()
186 WWDG->CR = CR_WDGA_Set | Counter; in WWDG_Enable()
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| /bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/src/ |
| A D | hk32f0xx_wwdg.c | 176 void WWDG_SetCounter(uint8_t Counter) in WWDG_SetCounter() argument
179 assert_param(IS_WWDG_COUNTER(Counter)); in WWDG_SetCounter()
182 WWDG->CR = Counter & BIT_MASK; in WWDG_SetCounter()
208 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
211 assert_param(IS_WWDG_COUNTER(Counter)); in WWDG_Enable()
212 WWDG->CR = WWDG_CR_WDGA | Counter; in WWDG_Enable()
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| /bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/ |
| A D | HAL_wwdg.c | 167 void WWDG_SetCounter(uint8_t Counter) in WWDG_SetCounter() argument
170 assert_param(IS_WWDG_COUNTER(Counter)); in WWDG_SetCounter()
173 WWDG->CR = Counter & BIT_Mask; in WWDG_SetCounter()
182 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
185 assert_param(IS_WWDG_COUNTER(Counter)); in WWDG_Enable()
186 WWDG->CR = CR_WDGA_Set | Counter; in WWDG_Enable()
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| /bsp/airm2m/air32f103/libraries/AIR32F10xLib/src/ |
| A D | air32f10x_wwdg.c | 149 void WWDG_SetCounter(uint8_t Counter) in WWDG_SetCounter() argument
152 assert_param(IS_WWDG_COUNTER(Counter)); in WWDG_SetCounter()
155 WWDG->CR = Counter & BIT_Mask; in WWDG_SetCounter()
164 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
167 assert_param(IS_WWDG_COUNTER(Counter)); in WWDG_Enable()
168 WWDG->CR = CR_WDGA_Set | Counter; in WWDG_Enable()
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| /bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/ |
| A D | n32l43x_wwdg.c | 171 void WWDG_SetCnt(uint8_t Counter) in WWDG_SetCnt() argument
174 assert_param(IS_WWDG_CNT(Counter)); in WWDG_SetCnt()
177 WWDG->CTRL = Counter & BIT_MASK; in WWDG_SetCnt()
185 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
188 assert_param(IS_WWDG_CNT(Counter)); in WWDG_Enable()
189 WWDG->CTRL = CTRL_ACTB_SET | Counter; in WWDG_Enable()
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| /bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/ |
| A D | n32g4fr_wwdg.c | 175 void WWDG_SetCnt(uint8_t Counter) in WWDG_SetCnt() argument
178 assert_param(IS_WWDG_CNT(Counter)); in WWDG_SetCnt()
181 WWDG->CTRL = Counter & BIT_MASK; in WWDG_SetCnt()
189 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
192 assert_param(IS_WWDG_CNT(Counter)); in WWDG_Enable()
193 WWDG->CTRL = CTRL_ACTB_SET | Counter; in WWDG_Enable()
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| /bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/ |
| A D | n32l40x_wwdg.c | 175 void WWDG_SetCnt(uint8_t Counter) in WWDG_SetCnt() argument
178 assert_param(IS_WWDG_CNT(Counter)); in WWDG_SetCnt()
181 WWDG->CTRL = Counter & BIT_MASK; in WWDG_SetCnt()
189 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
192 assert_param(IS_WWDG_CNT(Counter)); in WWDG_Enable()
193 WWDG->CTRL = CTRL_ACTB_SET | Counter; in WWDG_Enable()
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| /bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/ |
| A D | n32g45x_wwdg.c | 175 void WWDG_SetCnt(uint8_t Counter) in WWDG_SetCnt() argument
178 assert_param(IS_WWDG_CNT(Counter)); in WWDG_SetCnt()
181 WWDG->CTRL = Counter & BIT_MASK; in WWDG_SetCnt()
189 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
192 assert_param(IS_WWDG_CNT(Counter)); in WWDG_Enable()
193 WWDG->CTRL = CTRL_ACTB_SET | Counter; in WWDG_Enable()
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| /bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/ |
| A D | n32wb452_wwdg.c | 175 void WWDG_SetCnt(uint8_t Counter) in WWDG_SetCnt() argument
178 assert_param(IS_WWDG_CNT(Counter)); in WWDG_SetCnt()
181 WWDG->CTRL = Counter & BIT_MASK; in WWDG_SetCnt()
189 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
192 assert_param(IS_WWDG_CNT(Counter)); in WWDG_Enable()
193 WWDG->CTRL = CTRL_ACTB_SET | Counter; in WWDG_Enable()
|
| /bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/ |
| A D | n32g43x_wwdg.c | 175 void WWDG_SetCnt(uint8_t Counter) in WWDG_SetCnt() argument
178 assert_param(IS_WWDG_CNT(Counter)); in WWDG_SetCnt()
181 WWDG->CTRL = Counter & BIT_MASK; in WWDG_SetCnt()
189 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
192 assert_param(IS_WWDG_CNT(Counter)); in WWDG_Enable()
193 WWDG->CTRL = CTRL_ACTB_SET | Counter; in WWDG_Enable()
|
| /bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/ |
| A D | n32g45x_wwdg.c | 175 void WWDG_SetCnt(uint8_t Counter) in WWDG_SetCnt() argument
178 assert_param(IS_WWDG_CNT(Counter)); in WWDG_SetCnt()
181 WWDG->CTRL = Counter & BIT_MASK; in WWDG_SetCnt()
189 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
192 assert_param(IS_WWDG_CNT(Counter)); in WWDG_Enable()
193 WWDG->CTRL = CTRL_ACTB_SET | Counter; in WWDG_Enable()
|
| /bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/TOOLCHAIN_ARM/ |
| A D | startup_psoc6_01_cm4.s | 149 DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
150 DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
151 DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
152 DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
153 DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
154 DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
155 DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
156 DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
157 DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
158 DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
[all …]
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| /bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/libs/TARGET_CY8CKIT-062-WIFI-BT/COMPONENT_CM4/TOOLCHAIN_ARM/ |
| A D | startup_psoc6_01_cm4.s | 149 DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
150 DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
151 DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
152 DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
153 DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
154 DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
155 DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
156 DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
157 DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
158 DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
[all …]
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| /bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/TOOLCHAIN_ARM/ |
| A D | startup_psoc6_01_cm4.s | 149 DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
150 DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
151 DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
152 DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
153 DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
154 DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
155 DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
156 DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
157 DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
158 DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
[all …]
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| /bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/ |
| A D | startup_psoc6_02_cm4.s | 182 DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
183 DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
184 DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
185 DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
186 DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
187 DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
188 DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
189 DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
190 DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
191 DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
[all …]
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| /bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_CM4/TOOLCHAIN_ARM/ |
| A D | startup_psoc6_02_cm4.s | 182 DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
183 DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
184 DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
185 DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
186 DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
187 DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
188 DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
189 DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
190 DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
191 DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
[all …]
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| /bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/ |
| A D | startup_psoc6_02_cm4.s | 182 DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
183 DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
184 DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
185 DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
186 DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
187 DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
188 DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
189 DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
190 DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
191 DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
[all …]
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| /bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/ |
| A D | tae32f53xx_ll_wwdg.c | 90 assert_param(IS_WWDG_COUNTER(Init->Counter)); in LL_WWDG_Init()
96 WRITE_REG(Instance->CVR, Init->Counter); in LL_WWDG_Init()
179 LL_StatusETypeDef LL_WWDG_Refresh(WWDG_TypeDef *Instance, uint16_t Counter) in LL_WWDG_Refresh() argument
183 assert_param(IS_WWDG_COUNTER(Counter)); in LL_WWDG_Refresh()
186 __LL_WWDG_SET_COUNTER(Instance, Counter); in LL_WWDG_Refresh()
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| /bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/StdPeriph_Driver/src/ |
| A D | ch32f20x_wwdg.c | 85 void WWDG_SetCounter(uint8_t Counter) in WWDG_SetCounter() argument
87 WWDG->CTLR = Counter & BIT_Mask; in WWDG_SetCounter()
98 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
100 WWDG->CTLR = CTLR_WDGA_Set | Counter; in WWDG_Enable()
|
| /bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ |
| A D | ch32v10x_wwdg.c | 98 void WWDG_SetCounter(uint8_t Counter) in WWDG_SetCounter() argument
100 WWDG->CTLR = Counter & BIT_Mask; in WWDG_SetCounter()
112 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
114 WWDG->CTLR = CTLR_WDGA_Set | Counter; in WWDG_Enable()
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| /bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/StdPeriph_Driver/src/ |
| A D | ch32f10x_wwdg.c | 95 void WWDG_SetCounter(uint8_t Counter) in WWDG_SetCounter() argument
97 WWDG->CTLR = Counter & BIT_Mask; in WWDG_SetCounter()
108 void WWDG_Enable(uint8_t Counter) in WWDG_Enable() argument
110 WWDG->CTLR = CTLR_WDGA_Set | Counter; in WWDG_Enable()
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| /bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/arm/ |
| A D | startup_SAMD20.s | 84 DCD RTC_Handler ; 3 Real-Time Counter
94 DCD TC0_Handler ; 13 Basic Timer Counter 0
95 DCD TC1_Handler ; 14 Basic Timer Counter 1
96 DCD TC2_Handler ; 15 Basic Timer Counter 2
97 DCD TC3_Handler ; 16 Basic Timer Counter 3
98 DCD TC4_Handler ; 17 Basic Timer Counter 4
99 DCD TC5_Handler ; 18 Basic Timer Counter 5
100 DCD TC6_Handler ; 19 Basic Timer Counter 6
101 DCD TC7_Handler ; 20 Basic Timer Counter 7
|