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Searched refs:DCLR (Results 1 – 3 of 3) sorted by relevance

/bsp/rm48x50/HALCoGen/source/
A Dgio.c256 port->DCLR = 1U << bit; in gioSetBit()
345 port->DCLR = 1U << bit; in gioToggleBit()
/bsp/rm48x50/HALCoGen/include/
A Dreg_gio.h67 uint32 DCLR; /**< 0x0010: Data Output Clear Register */ member
A Dreg_het.h64 uint32 DCLR; /**< 0x005C: Data output clear register */ member

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