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Searched refs:DFSR (Results 1 – 25 of 374) sorted by relevance

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/bsp/rockchip/common/rk_hal/lib/hal/src/pm/
A Dhal_pm_cpu.c233 scbSave.DFSR = SCB->DFSR; in HAL_SCB_SuspendSave()
255 SCB->DFSR = scbSave.DFSR; in HAL_SCB_ResumeRestore()
/bsp/microchip/samc21/bsp/hri/
A Dhri_systemcontrol_c21.h454 ((Systemcontrol *)hw)->DFSR.reg |= mask; in hri_systemcontrol_set_DFSR_reg()
462 tmp = ((Systemcontrol *)hw)->DFSR.reg; in hri_systemcontrol_get_DFSR_reg()
470 ((Systemcontrol *)hw)->DFSR.reg = data; in hri_systemcontrol_write_DFSR_reg()
477 ((Systemcontrol *)hw)->DFSR.reg &= ~mask; in hri_systemcontrol_clear_DFSR_reg()
484 ((Systemcontrol *)hw)->DFSR.reg ^= mask; in hri_systemcontrol_toggle_DFSR_reg()
490 return ((Systemcontrol *)hw)->DFSR.reg; in hri_systemcontrol_read_DFSR_reg()
/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/
A Dcore_cm3.h318 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
A Dcore_cm4.h347 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/
A Dcore_cm3.h198 …__IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register … member
/bsp/smartfusion2/CMSIS/
A Dcore_cm3.h173 …__IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register … member
/bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/CMSIS/
A Dcore_cm3.h167 …__IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register … member
/bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/CMSIS/
A Dcore_cm3.h167 …__IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register … member
/bsp/efm32/Libraries/CMSIS/Include/
A Dcore_cm3.h325 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
/bsp/fujitsu/mb9x/mb9bf506r/libraries/CMSIS/Include/
A Dcore_cm3.h325 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/
A Dcore_cm3.h340 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
A Dcore_sc300.h331 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
/bsp/CME_M7/CMSIS/CMSIS/Include/
A Dcore_sc300.h331 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
A Dcore_cm3.h340 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
/bsp/samd21/sam_d2x_asflib/CMSIS/Include/
A Dcore_cm3.h360 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
A Dcore_sc300.h360 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/
A Dcore_cm3.h340 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
/bsp/mm32l07x/Libraries/CMSIS/CORE/
A Dcore_cm3.h340 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
A Dcore_sc300.h331 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
/bsp/synwit/libraries/SWM320_CSL/CMSIS/CoreSupport/
A Dcore_cm3.h360 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
/bsp/mm32l07x/Libraries/CMSIS/IAR_CORE/
A Dcore_cm3.h360 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
A Dcore_sc300.h360 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
/bsp/mm32l3xx/Libraries/CMSIS/IAR_CORE/
A Dcore_cm3.h360 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
A Dcore_sc300.h360 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member
/bsp/mm32l3xx/Libraries/CMSIS/KEIL_CORE/
A Dcore_cm3.h340 …__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register … member

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