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Searched refs:DIV (Results 1 – 25 of 88) sorted by relevance

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/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/
A Dn32g45x_rcc.h296 …(((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK…
297 …|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCC…
298 …|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCC…
349 …(((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) …
350 …|| ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) …
351 …|| ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) …
352 …|| ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12)…
353 …|| ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15)…
354 …|| ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18)…
355 …|| ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21)…
[all …]
/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/
A Dn32g4fr_rcc.h296 …(((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK…
297 …|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCC…
298 …|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCC…
349 …(((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) …
350 …|| ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) …
351 …|| ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) …
352 …|| ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12)…
353 …|| ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15)…
354 …|| ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18)…
355 …|| ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21)…
[all …]
/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/
A Dn32wb452_rcc.h296 …(((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK…
297 …|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCC…
298 …|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCC…
349 …(((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) …
350 …|| ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) …
351 …|| ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) …
352 …|| ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12)…
353 …|| ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15)…
354 …|| ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18)…
355 …|| ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21)…
[all …]
/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/
A Dn32g45x_rcc.h296 …(((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK…
297 …|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCC…
298 …|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCC…
353 …(((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) …
354 …|| ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) …
355 …|| ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) …
356 …|| ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12)…
357 …|| ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15)…
358 …|| ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18)…
359 …|| ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21)…
[all …]
A Dn32g45x_xfmc.h542 #define IS_XFMC_NOR_SRAM_CLK_DIV(DIV) ( ((DIV) >= XFMC_NOR_SRAM_CLK_DIV_2) \ argument
543 && ((DIV) <= XFMC_NOR_SRAM_CLK_DIV_16) )
/bsp/synwit/libraries/SWM341_CSL/SWM341_StdPeriph_Driver/
A DSWM341_div.h18 DIV->DIVIDEND = dividend; in DIV_UDiv()
19 DIV->DIVISOR = divisor; in DIV_UDiv()
34 DIV->DIVIDEND = dividend; in DIV_SDiv()
35 DIV->DIVISOR = divisor; in DIV_SDiv()
62 *quotient = DIV->QUO; in DIV_UDiv_Result()
63 *remainder = DIV->REMAIN; in DIV_UDiv_Result()
76 *quotient = DIV->QUO & 0x7FFFFFFF; in DIV_SDiv_Result()
93 DIV->RADICAND = radicand; in DIV_Root()
119 if(DIV->CR & DIV_CR_ROOTMOD_Msk) in DIV_Root_Result()
121 return DIV->ROOT; in DIV_Root_Result()
[all …]
A DSWM341_div.c36 case ((uint32_t)DIV): in DIV_Init()
/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/
A Dn32l43x_rcc.h358 …(((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK…
359 …|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCC…
360 …|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCC…
411 …(((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) …
412 …|| ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) …
413 …|| ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) …
414 …|| ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12)…
415 …|| ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15)…
416 …|| ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18)…
417 …|| ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21)…
[all …]
/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/
A Dn32l40x_rcc.h358 …(((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK…
359 …|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCC…
360 …|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCC…
411 …(((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) …
412 …|| ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) …
413 …|| ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) …
414 …|| ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12)…
415 …|| ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15)…
416 …|| ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18)…
417 …|| ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21)…
[all …]
/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/
A Dn32g43x_rcc.h358 …(((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK…
359 …|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCC…
360 …|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCC…
411 …(((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) …
412 …|| ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) …
413 …|| ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) …
414 …|| ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12)…
415 …|| ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15)…
416 …|| ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18)…
417 …|| ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21)…
[all …]
/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/
A Dft32f0xx_div.c37 DIV->DID = divedent; in DivS32ByS16()
38 DIV->DIS = dividor; in DivS32ByS16()
50 pResult -> DIV_quotient = DIV-> QUO; in DivS32ByS16()
51 pResult -> DIV_remainder = DIV-> REM; in DivS32ByS16()
115 DIV->SC |= DIV_IT; in DIV_ITConfig()
120 DIV->SC &= (~(uint32_t)DIV_IT); in DIV_ITConfig()
141 if ((DIV->SC & DIV_FLAG) != (uint32_t)RESET) in DIV_GetFlagStatus()
168 DIV->SC |= (uint32_t)(DIV_FLAG<<8); in DIV_ClearFlag()
188 enablestatus = (uint32_t)((DIV->SC>>1) & DIV_IT); in DIV_GetITStatus()
191 if (((uint32_t)(DIV->SC & DIV_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) in DIV_GetITStatus()
[all …]
/bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Src/
A DHAL_DIV.c10 DIV->REMAIN = 0; in hardwareNN_Div_q32()
11 DIV->DIVISOR = *c; in hardwareNN_Div_q32()
15 DIV->DIVIDENED = *p; in hardwareNN_Div_q32()
17 while((DIV->STATUS&0x01)!=0x01); in hardwareNN_Div_q32()
18 DIV->STATUS = 0x01; in hardwareNN_Div_q32()
19 (*(q+i)) = (UINT32)DIV->QUOTIENT; in hardwareNN_Div_q32()
21 (*a) = DIV->REMAIN; in hardwareNN_Div_q32()
/bsp/airm2m/air105/libraries/HAL_Driver/Inc/
A Dair105_sysctrl.h94 #define IS_GET_SYSCTRL_PLL_DIV(DIV) (((DIV) == SYSCTRL_PLL_Div_None) || \ argument
95 ((DIV) == SYSCTRL_PLL_Div2) || \
96 ((DIV) == SYSCTRL_PLL_Div4))
100 #define IS_GET_SYSCTRL_HCLK_DIV(DIV) (((DIV) == SYSCTRL_HCLK_Div_None) || \ argument
101 ((DIV) == SYSCTRL_HCLK_Div2))
105 #define IS_GET_SYSCTRL_PCLK_DIV(DIV) (((DIV) == SYSCTRL_PCLK_Div2) || \ argument
106 ((DIV) == SYSCTRL_PCLK_Div4))
A Dair105_dcmi.h189 #define IS_DCMI_CLOCK_DIV(DIV) (((DIV) == DCMI_Clock_Div2) ||\ argument
190 ((DIV) == DCMI_Clock_Div4) ||\
191 ((DIV) == DCMI_Clock_Div6) ||\
192 ((DIV) == DCMI_Clock_Div8) ||\
193 ((DIV) == DCMI_Clock_Div10) ||\
194 ((DIV) == DCMI_Clock_Div12) ||\
195 ((DIV) == DCMI_Clock_Div14) ||\
196 ((DIV) == DCMI_Clock_Div16))
/bsp/CME_M7/StdPeriph_Driver/inc/
A Dcmem7_can.h75 #define IS_CAN_CDR_DIV(DIV) (((DIV) == CAN_CDR_DIV_1_2) || \ argument
76 ((DIV) == CAN_CDR_DIV_1_4) || \
77 … ((DIV) == CAN_CDR_DIV_1_6) || \
78 … ((DIV) == CAN_CDR_DIV_1_8) || \
79 … ((DIV) == CAN_CDR_DIV_1_10) || \
80 … ((DIV) == CAN_CDR_DIV_1_12) || \
81 … ((DIV) == CAN_CDR_DIV_1_14) || \
82 ((DIV) == CAN_CDR_DIV_1_1))
/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/
A Dft32f0xx_crs.h102 #define IS_CRS_SYNC_DIV(DIV) (((DIV) == CRS_SYNC_Div1) || ((DIV) == CRS_SYNC_Div2) ||\ argument
103 ((DIV) == CRS_SYNC_Div4) || ((DIV) == CRS_SYNC_Div8) || \
104 ((DIV) == CRS_SYNC_Div16) || ((DIV) == CRS_SYNC_Div32) || \
105 ((DIV) == CRS_SYNC_Div64) || ((DIV) == CRS_SYNC_Div128))
/bsp/airm2m/air32f103/libraries/AIR32F10xLib/inc/
A Dair32f10x_trng.h32 #define IS_TRNG_DIV(DIV) (((DIV) == TRNG_Periph_Div_None) || \ argument
33 ((DIV) == TRNG_Periph_Div2) || \
34 ((DIV) == TRNG_Periph_Div4) || \
35 ((DIV) == TRNG_Periph_Div8))
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_pllctlv2_drv.c85 ptr->PLL[pll].DIV[div_index] = in pllctlv2_set_postdiv()
86 …(ptr->PLL[pll].DIV[div_index] & ~PLLCTLV2_PLL_DIV_DIV_MASK) | PLLCTLV2_PLL_DIV_DIV_SET(div_value) | in pllctlv2_set_postdiv()
107 uint32_t postdiv = PLLCTLV2_PLL_DIV_DIV_GET(ptr->PLL[pll].DIV[div_index]); in pllctlv2_get_pll_postdiv_freq_in_hz()
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/
A Dht32f5xxxx_rstcu.h91 unsigned long DIV :1; // Bit 16 member
104 unsigned long DIV :1; // Bit 24 member
A Dht32f5xxxx_ckcu.h425 unsigned long DIV :1; // Bit 24 member
899 #define CKCU_SetADCPrescaler(DIV) CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADC0, DIV) argument
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/
A Dht32f1xxxx_sdio.h128 #define IS_SDIO_CLOC_DIV(DIV) ((DIV > 0) && (DIV < 256)) argument
/bsp/Vango/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/
A Dlib_rtc.c755 RTC->DIV = RTC_DIV_RTCDIV; in RTC_PLLDIVConfig()
759 RTC->DIV = CLK_GetPLLLFreq()/2/nfrequency - 1; in RTC_PLLDIVConfig()
767 RTC->DIV = RTC_DIV_RTCDIV; in RTC_PLLDIVConfig()
771 RTC->DIV = CLK_GetPLLLFreq()/2/nfrequency - 1; in RTC_PLLDIVConfig()
/bsp/apollo2/libraries/drivers/hal/
A Dam_hal_pdm.h154 #define AM_HAL_PDM_PCFG_MCLKDIV(DIV) AM_REG_PDM_PCFG_MCLKDIV(DIV) argument
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/
A Dfm33lc0xx_fl_divas.c40 #define IS_DIVAS_ALL_INSTANCE(INTENCE) ((INTENCE) == DIV)
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/
A Dht32f5xxxx_div.c60 RSTCUReset.Bit.DIV = 1; in DIV_DeInit()

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