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Searched refs:DIV0 (Results 1 – 2 of 2) sorted by relevance

/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_pllctl_drv.h292 return PLLCTL_PLL_DIV0_DIV_GET(ptr->PLL[pll].DIV0) + 1; in pllctl_get_div()
318 ptr->PLL[pll].DIV0 = (ptr->PLL[pll].DIV0 & ~(PLLCTL_PLL_DIV0_DIV_MASK)) in pllctl_set_div()
341 return ptr->PLL[pll].DIV0 & PLLCTL_PLL_DIV0_RESPONSE_MASK; in pllctl_div_is_stable()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/
A Dhpm_pllctl_regs.h24 __RW uint32_t DIV0; /* 0xC0: PLLx divider0 control */ member

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