Searched refs:DLH (Results 1 – 16 of 16) sorted by relevance
54 pReg->DLH = (DivLatch >> 8) & 0xff; in UART_SetBaudRate()142 pUartSave->DLH = pReg->DLH; in HAL_UART_Suspend()165 pReg->DLH = pUartSave->DLH; in HAL_UART_Resume()
62 uint32_t DLH; member601 pUartSave->DLH = pUart->DLH; in SOC_UartSave()613 pUart->DLH = pUartSave->DLH; in SOC_UartRestore()
75 …__IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section registe… member
100 addr->DLH = (divisor >> 8) & 0xff; in csi_usart_config_baudrate()
88 …__IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section registe… member
104 addr->DLH = (divisor >> 8) & 0xff; in dw_usart_set_baudrate()
81 uart_base->DLH = (divisor >> 8U) & 0xFFU; in dw_uart_config_baudrate()
165 Uart->OFFSET_4.DLH = ((tmpBaudRateDiv >> 8) & 0x00FF); in Uart_BaseInit()225 Uart->OFFSET_4.DLH = 0; in Uart_DeInit()587 Uart->OFFSET_4.DLH = ((tmpBaudRateDiv >> 8) & 0x00FF); in Uart_ChangeBR()
234 uint32_t DLH; member
119 …__IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section registe…
279 …__IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section registe… member
360 _uart[channel]->DLH = dlh; in rt_uart_configure()
230 #define __LL_UART_DivLatchHigh_Write(__UART__, val) WRITE_REG((__UART__)->DLH, (val & UART_DLH_DLH_…
268 __IO uint32_t DLH; member
355 … __IOM uint32_t DLH; /*!< Address offset: 0x04: Divisor Latch High */ member
407 __IO uint32_t DLH; /* Address Offset: 0x0004 */ member
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