| /bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/ |
| A D | MM32L3xx_lib_version.txt | 56 #define DMA1_BASE (AHBPERIPH_BASE + 0x02c0)
65 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
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| /bsp/mm32f327x/Libraries/MM32F327x/Include/ |
| A D | reg_dma.h | 47 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000) ///< Base Address: … macro
87 #define DMA1 ((DMA_TypeDef*) DMA1_BASE)
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| /bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/ |
| A D | stm32l1xx_ll_dma.h | 49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
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| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/ |
| A D | bl808_memorymap.h | 104 #define DMA1_BASE ((uint32_t)0x20071000) macro
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| /bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/ |
| A D | ft32f030x6.h | 687 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) macro
688 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
689 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
690 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
691 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
692 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
693 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
694 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
747 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | ft32f030x8.h | 725 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) macro
726 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
727 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
728 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
729 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
730 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
731 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
732 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
786 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | ft32f072x8.h | 734 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) macro
735 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
736 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
737 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
738 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
739 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
740 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
741 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
795 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | ft32f032x8.h | 736 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) macro
737 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
738 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
739 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
740 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
741 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
742 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
743 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
798 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | ft32f032x6.h | 736 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) macro
737 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
738 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
739 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
740 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
741 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
742 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
743 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
798 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | ft32f072xb.h | 785 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) macro
786 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
787 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
788 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
789 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
790 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
791 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
792 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
850 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| /bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Include/ |
| A D | apm32f0xx.h | 5501 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) macro
5502 #define DMA1_CHANNEL_1_BASE (DMA1_BASE + 0x00000008)
5503 #define DMA1_CHANNEL_2_BASE (DMA1_BASE + 0x0000001C)
5504 #define DMA1_CHANNEL_3_BASE (DMA1_BASE + 0x00000030)
5505 #define DMA1_CHANNEL_4_BASE (DMA1_BASE + 0x00000044)
5506 #define DMA1_CHANNEL_5_BASE (DMA1_BASE + 0x00000058)
5507 #define DMA1_CHANNEL_6_BASE (DMA1_BASE + 0x0000006C)
5508 #define DMA1_CHANNEL_7_BASE (DMA1_BASE + 0x00000080)
5567 #define DMA1 ((DMA_T*) DMA1_BASE)
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| /bsp/apm32/libraries/APM32F4xx_Library/Device/Geehy/APM32F4xx/Include/ |
| A D | apm32f4xx.h | 7267 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) macro
7268 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
7269 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
7270 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
7271 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
7272 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
7273 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
7274 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
7275 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
7388 #define DMA1 ((DMA_T *) DMA1_BASE)
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| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/ |
| A D | bl808.h | 448 #define DMA1_BASE ((uint32_t)0x20071000) macro
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| /bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/ |
| A D | hk32f030x4x6x8.h | 493 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) macro
494 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
495 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
496 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
497 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
498 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
546 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | hk32f031x4x6.h | 484 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) macro
485 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
486 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
487 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
488 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
489 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
533 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | hk32f04ax4x6x8.h | 525 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) macro
526 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
527 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
528 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
529 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
530 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
577 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| /bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/ |
| A D | stm32l100xb.h | 625 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL) macro
626 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
627 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
628 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
629 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
630 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
631 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
632 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
695 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | stm32l100xba.h | 625 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL) macro
626 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
627 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
628 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
629 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
630 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
631 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
632 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
695 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | stm32l151xb.h | 625 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL) macro
626 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
627 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
628 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
629 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
630 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
631 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
632 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
695 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | stm32l151xba.h | 625 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL) macro
626 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
627 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
628 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
629 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
630 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
631 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
632 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
695 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | stm32l152xb.h | 641 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL) macro
642 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
643 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
644 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
645 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
646 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
647 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
648 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
712 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | stm32l152xba.h | 626 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL) macro
627 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
628 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
629 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
630 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
631 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
632 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
633 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
697 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | stm32l100xc.h | 654 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL) macro
655 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
656 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
657 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
658 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
659 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
660 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
661 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
731 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | stm32l162xdx.h | 739 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL) macro
740 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
741 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
742 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
743 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
744 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
745 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
746 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
827 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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| A D | stm32l162xe.h | 739 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL) macro
740 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
741 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
742 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
743 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
744 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
745 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
746 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
827 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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