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Searched refs:DMA1_Channel3_IRQn (Results 1 – 25 of 62) sorted by relevance

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/bsp/at32/libraries/rt_drivers/config/a403a/
A Ddma_config.h44 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
49 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
54 #define I2C3_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/at32/libraries/rt_drivers/config/f403a_407/
A Ddma_config.h44 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
49 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
54 #define I2C3_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/
A Ddma_config.h40 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
45 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/at32/libraries/rt_drivers/config/f413/
A Ddma_config.h39 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
44 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/at32/libraries/rt_drivers/config/f415/
A Ddma_config.h39 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
44 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/at32/libraries/rt_drivers/config/m412_416/
A Ddma_config.h59 #define SPI2_RX_DMA_IRQ DMA1_Channel3_IRQn
66 #define I2C1_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/at32/libraries/rt_drivers/config/a423/
A Ddma_config.h73 #define SPI2_RX_DMA_IRQ DMA1_Channel3_IRQn
80 #define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn
87 #define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/at32/libraries/rt_drivers/config/f402_405/
A Ddma_config.h73 #define SPI2_RX_DMA_IRQ DMA1_Channel3_IRQn
80 #define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn
87 #define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/at32/libraries/rt_drivers/config/f423/
A Ddma_config.h73 #define SPI2_RX_DMA_IRQ DMA1_Channel3_IRQn
80 #define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn
87 #define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/at32/libraries/rt_drivers/config/f45x/
A Ddma_config.h73 #define SPI2_RX_DMA_IRQ DMA1_Channel3_IRQn
80 #define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn
87 #define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/at32/libraries/rt_drivers/config/f435_437/
A Ddma_config.h73 #define SPI2_RX_DMA_IRQ DMA1_Channel3_IRQn
80 #define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn
87 #define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/
A Ddma_config.h38 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
44 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/
A Ddma_config.h47 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
52 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/
A Ddma_config.h46 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
56 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/
A Ddma_config.h47 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
57 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/
A Ddma_config.h47 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
57 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/
A Ddma_config.h47 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
57 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/
A Dgd32vf103.h162DMA1_Channel3_IRQn = 78, /*!< DMA1 channel3 global interrupt … enumerator
/bsp/gd32/arm/libraries/gd32_drivers/
A Ddrv_sdio.h54 #define SDIO_DMA_IRQ DMA1_Channel3_IRQn
/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_common.h109DMA1_Channel3_IRQn = 13, ///< DMA1 channel 3 g… enumerator
/bsp/n32g452xx/Libraries/rt_drivers/
A Ddrv_usart.c374 DMA1_Channel3_IRQn,
/bsp/wch/risc-v/Libraries/ch32_drivers/
A Ddrv_usart_v2.c1102 uart_obj[UART3_INDEX].dma_rx.handle.dma_irq = DMA1_Channel3_IRQn; in ch32_uart_get_config()
/bsp/n32/libraries/n32_drivers/
A Ddrv_usart_v2.c1431 uart_obj[UART3_INDEX].dma_rx.handle.dma_irq = DMA1_Channel3_IRQn; in n32_uart_get_config()
/bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Include/
A Dch32v10x.h50 DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ enumerator
/bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/
A Dch32v10x.h50 DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ enumerator

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