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Searched refs:DMA1_Channel4_BASE (Results 1 – 25 of 56) sorted by relevance

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/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_dma.h51 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) ///< Base Address: … macro
91 #define DMA1_ch4 ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE)
97 #define DMA1_Channel4 ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE)
/bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/
A DMM32L3xx_lib_version.txt60 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0108)
69 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
/bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/src/
A DHAL_dma.c134 case DMA1_Channel4_BASE: in DMA_DeInit()
/bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/src/
A DHAL_dma.c137 case DMA1_Channel4_BASE: in DMA_DeInit()
/bsp/tkm32F499/Libraries/Hal_lib/src/
A DHAL_dma_bak.c138 case DMA1_Channel4_BASE:
/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/
A DHAL_dma.c137 case DMA1_Channel4_BASE: in DMA_DeInit()
/bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/inc/
A DHAL_dma.h71 ((*(uint32_t*)&(PERIPH)) == DMA1_Channel4_BASE) || \
/bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/inc/
A DHAL_dma.h71 ((*(uint32_t*)&(PERIPH)) == DMA1_Channel4_BASE) || \
/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/
A DHAL_dma.h71 ((*(uint32_t*)&(PERIPH)) == DMA1_Channel4_BASE) || \
/bsp/tkm32F499/Libraries/Hal_lib/inc/
A DHAL_dma.h71 ((*(uint32_t*)&(PERIPH)) == DMA1_Channel4_BASE) || \
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_ll_dma.h52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/
A Dft32f030x6.h691 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) macro
751 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
A Dft32f030x8.h729 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) macro
790 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
A Dft32f072x8.h738 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) macro
799 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
A Dft32f032x8.h740 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) macro
802 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
A Dft32f032x6.h740 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) macro
802 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
A Dft32f072xb.h789 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) macro
854 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
/bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Include/
A Dch32v10x.h564 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) macro
633 #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
/bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/
A Dch32v10x.h564 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) macro
633 #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
/bsp/mm32l3xx/Libraries/MM32L3xx/Include/
A DMM32L3xx.h985 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) macro
1048 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
/bsp/mm32f103x/Libraries/MM32F103/Include/
A DMM32F103.h994 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) macro
1057 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
/bsp/apm32/libraries/APM32S10x_Library/Device/Geehy/APM32S10x/Include/
A Dapm32s10x.h4399 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) macro
4432 #define DMA1_Channel4 ((DMA_Channel_T *) DMA1_Channel4_BASE)
/bsp/tkm32F499/Libraries/CMSIS_and_startup/
A Dtk499.h1234 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x6044) macro
1366 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
/bsp/mm32l07x/Libraries/MM32L0xx/Include/
A DMM32L0xx.h937 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) macro
991 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f030x4x6x8.h497 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) macro
550 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

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