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Searched refs:DMA2 (Results 1 – 25 of 130) sorted by relevance

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/bsp/mm32/libraries/HAL_Drivers/config/mm32f3277g8p/
A Ddma_config.h122 #define SPI3_RX_DMA_INSTANCE DMA2
128 #define UART5_RX_DMA_INSTANCE DMA2
134 #define UART7_RX_DMA_INSTANCE DMA2
143 #define SPI3_TX_DMA_INSTANCE DMA2
149 #define UART5_TX_DMA_INSTANCE DMA2
155 #define UART7_TX_DMA_INSTANCE DMA2
164 #define UART4_RX_DMA_INSTANCE DMA2
170 #define UART8_RX_DMA_INSTANCE DMA2
179 #define UART6_TX_DMA_INSTANCE DMA2
188 #define UART4_TX_DMA_INSTANCE DMA2
[all …]
/bsp/apm32/libraries/APM32E10x_Library/APM32E10x_StdPeriphDriver/src/
A Dapm32e10x_dma.c88 DMA2->INTFCLR |= 0xFFFFFFF0; in DMA_Reset()
92 DMA2->INTFCLR |= 0xFFFFFF0F; in DMA_Reset()
96 DMA2->INTFCLR |= 0xFFFFF0FF; in DMA_Reset()
100 DMA2->INTFCLR |= 0xFFFF0FFF; in DMA_Reset()
104 DMA2->INTFCLR |= 0xFFF0FFFF; in DMA_Reset()
318 if((DMA2->INTSTS & flag ) != RESET ) in DMA_ReadStatusFlag()
400 DMA2->INTFCLR = flag; in DMA_ClearStatusFlag()
469 if((DMA2->INTSTS & flag ) != RESET ) in DMA_ReadIntFlag()
550 DMA2->INTFCLR = flag; in DMA_ClearIntFlag()
/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/
A Dapm32f10x_dma.c88 DMA2->INTFCLR |= 0xFFFFFFF0; in DMA_Reset()
92 DMA2->INTFCLR |= 0xFFFFFF0F; in DMA_Reset()
96 DMA2->INTFCLR |= 0xFFFFF0FF; in DMA_Reset()
100 DMA2->INTFCLR |= 0xFFFF0FFF; in DMA_Reset()
104 DMA2->INTFCLR |= 0xFFF0FFFF; in DMA_Reset()
318 if ((DMA2->INTSTS & flag) != RESET) in DMA_ReadStatusFlag()
403 DMA2->INTFCLR = flag; in DMA_ClearStatusFlag()
474 if ((DMA2->INTSTS & flag) != RESET) in DMA_ReadIntFlag()
559 DMA2->INTFCLR = flag; in DMA_ClearIntFlag()
/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/
A Dapm32f0xx_dma.c123 DMA2->INTFCLR = (uint32_t)0x0000000F; in DMA_Reset()
127 DMA2->INTFCLR = (uint32_t)0x000000F0; in DMA_Reset()
131 DMA2->INTFCLR = (uint32_t)0x00000F00; in DMA_Reset()
135 DMA2->INTFCLR = (uint32_t)0x0000F000; in DMA_Reset()
139 DMA2->INTFCLR = (uint32_t)0x000F0000; in DMA_Reset()
457 status = DMA2->INTSTS & ((uint32_t)flag & 0x000FFFFF); in DMA_ReadStatusFlag()
535 DMA2->INTFCLR |= (uint32_t)(flag & 0x000FFFFF); in DMA_ClearStatusFlag()
607 status = DMA2->INTSTS & ((uint32_t)flag & 0x000FFFFF); in DMA_ReadIntFlag()
684 DMA2->INTFCLR |= (uint32_t)(flag & 0x000FFFFF); in DMA_ClearIntFlag()
/bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/
A Dapm32f4xx_dma.c95 DMA2->LIFCLR |= 0x0000003D; in DMA_Reset()
99 DMA2->LIFCLR |= 0X00000F40; in DMA_Reset()
103 DMA2->LIFCLR |= 0x003D0000; in DMA_Reset()
107 DMA2->LIFCLR |= 0X0F400000; in DMA_Reset()
111 DMA2->HIFCLR |= 0x0000003D; in DMA_Reset()
115 DMA2->HIFCLR |= 0X00000F40; in DMA_Reset()
119 DMA2->HIFCLR |= 0x003D0000; in DMA_Reset()
423 dma = DMA2; in DMA_ReadStatusFlag()
476 dma = DMA2; in DMA_ClearStatusFlag()
571 dma = DMA2; in DMA_ReadIntFlag()
[all …]
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_hal_tim_ex.h61 #if defined(DMA2)
66 #if defined(DMA2)
71 #if defined(DMA2)
80 #if defined(DMA2)
91 #if defined(DMA2)
124 #if defined(DMA2)
A Dstm32l1xx_ll_dma.h35 #if defined (DMA1) || defined (DMA2)
358 #if defined(DMA2)
360 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
370 #if defined (DMA2)
418 #if defined (DMA2)
422 …(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D…
424 …(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D…
426 …(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D…
428 …(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D…
430 …(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D…
[all …]
/bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/StdPeriph_Driver/src/
A Dch32f20x_dma.c87 DMA2->INTFCR |= DMA2_Channel1_IT_Mask; in DMA_DeInit()
91 DMA2->INTFCR |= DMA2_Channel2_IT_Mask; in DMA_DeInit()
95 DMA2->INTFCR |= DMA2_Channel3_IT_Mask; in DMA_DeInit()
99 DMA2->INTFCR |= DMA2_Channel4_IT_Mask; in DMA_DeInit()
103 DMA2->INTFCR |= DMA2_Channel5_IT_Mask; in DMA_DeInit()
107 DMA2->INTFCR |= DMA2_Channel6_IT_Mask; in DMA_DeInit()
111 DMA2->INTFCR |= DMA2_Channel7_IT_Mask; in DMA_DeInit()
349 tmpreg = DMA2->INTFR ; in DMA_GetFlagStatus()
455 DMA2->INTFCR = DMAy_FLAG; in DMA_ClearFlag()
553 tmpreg = DMA2->INTFR; in DMA_GetITStatus()
[all …]
/bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/
A Dch32v10x_dma.c83 DMA2->INTFCR |= DMA2_Channel1_IT_Mask; in DMA_DeInit()
87 DMA2->INTFCR |= DMA2_Channel2_IT_Mask; in DMA_DeInit()
91 DMA2->INTFCR |= DMA2_Channel3_IT_Mask; in DMA_DeInit()
95 DMA2->INTFCR |= DMA2_Channel4_IT_Mask; in DMA_DeInit()
101 DMA2->INTFCR |= DMA2_Channel5_IT_Mask; in DMA_DeInit()
312 tmpreg = DMA2->INTFR; in DMA_GetFlagStatus()
392 DMA2->INTFCR = DMAy_FLAG; in DMA_ClearFlag()
465 tmpreg = DMA2->INTFR; in DMA_GetITStatus()
544 DMA2->INTFCR = DMAy_IT; in DMA_ClearITPendingBit()
/bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/StdPeriph_Driver/src/
A Dch32f10x_dma.c80 DMA2->INTFCR |= DMA2_Channel1_IT_Mask; in DMA_DeInit()
84 DMA2->INTFCR |= DMA2_Channel2_IT_Mask; in DMA_DeInit()
88 DMA2->INTFCR |= DMA2_Channel3_IT_Mask; in DMA_DeInit()
92 DMA2->INTFCR |= DMA2_Channel4_IT_Mask; in DMA_DeInit()
98 DMA2->INTFCR |= DMA2_Channel5_IT_Mask; in DMA_DeInit()
296 tmpreg = DMA2->INTFR ; in DMA_GetFlagStatus()
374 DMA2->INTFCR = DMAy_FLAG; in DMA_ClearFlag()
444 tmpreg = DMA2->INTFR; in DMA_GetITStatus()
521 DMA2->INTFCR = DMAy_IT; in DMA_ClearITPendingBit()
/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/
A Dhal_dma.c56 DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5); in DMA_DeInit()
181 return (DMA2->ISR & flag) ? SET : RESET; in DMA_GetFlagStatus()
204 DMA2->IFCR = flag; in DMA_ClearFlag()
228 return (DMA2->ISR & it) ? SET : RESET; in DMA_GetITStatus()
251 DMA2->IFCR = it; in DMA_ClearITPendingBit()
308 DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5); in exDMA_ClearITPendingBit()
309 DMA2->IFCR = it; in exDMA_ClearITPendingBit()
/bsp/airm2m/air32f103/libraries/AIR32F10xLib/src/
A Dair32f10x_dma.c142 DMA2->IFCR |= DMA2_Channel1_IT_Mask; in DMA_DeInit()
147 DMA2->IFCR |= DMA2_Channel2_IT_Mask; in DMA_DeInit()
152 DMA2->IFCR |= DMA2_Channel3_IT_Mask; in DMA_DeInit()
157 DMA2->IFCR |= DMA2_Channel4_IT_Mask; in DMA_DeInit()
164 DMA2->IFCR |= DMA2_Channel5_IT_Mask; in DMA_DeInit()
421 tmpreg = DMA2->ISR ; in DMA_GetFlagStatus()
508 DMA2->IFCR = DMAy_FLAG; in DMA_ClearFlag()
583 tmpreg = DMA2->ISR; in DMA_GetITStatus()
669 DMA2->IFCR = DMAy_IT; in DMA_ClearITPendingBit()
/bsp/tkm32F499/Libraries/Hal_lib/src/
A DHAL_dma.c166 DMA2->IFCR |= DMA2_Channel1_IT_Mask; in DMA_DeInit()
171 DMA2->IFCR |= DMA2_Channel2_IT_Mask; in DMA_DeInit()
176 DMA2->IFCR |= DMA2_Channel3_IT_Mask; in DMA_DeInit()
181 DMA2->IFCR |= DMA2_Channel4_IT_Mask; in DMA_DeInit()
188 DMA2->IFCR |= DMA2_Channel5_IT_Mask; in DMA_DeInit()
445 tmpreg = DMA2->ISR ; in DMA_GetFlagStatus()
532 DMA2->IFCR = DMAy_FLAG; in DMA_ClearFlag()
607 tmpreg = DMA2->ISR; in DMA_GetITStatus()
693 DMA2->IFCR = DMAy_IT; in DMA_ClearITPendingBit()
/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/
A Dn32g4fr_dma.c182 DMA2->INTCLR |= DMA2_CH1_INT_MASK; in DMA_DeInit()
187 DMA2->INTCLR |= DMA2_CH2_INT_MASK; in DMA_DeInit()
192 DMA2->INTCLR |= DMA2_CH3_INT_MASK; in DMA_DeInit()
197 DMA2->INTCLR |= DMA2_CH4_INT_MASK; in DMA_DeInit()
202 DMA2->INTCLR |= DMA2_CH5_INT_MASK; in DMA_DeInit()
207 DMA2->INTCLR |= DMA2_CH6_INT_MASK; in DMA_DeInit()
212 DMA2->INTCLR |= DMA2_CH7_INT_MASK; in DMA_DeInit()
219 DMA2->INTCLR |= DMA2_CH8_INT_MASK; in DMA_DeInit()
/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/
A Dn32wb452_dma.c182 DMA2->INTCLR |= DMA2_CH1_INT_MASK; in DMA_DeInit()
187 DMA2->INTCLR |= DMA2_CH2_INT_MASK; in DMA_DeInit()
192 DMA2->INTCLR |= DMA2_CH3_INT_MASK; in DMA_DeInit()
197 DMA2->INTCLR |= DMA2_CH4_INT_MASK; in DMA_DeInit()
202 DMA2->INTCLR |= DMA2_CH5_INT_MASK; in DMA_DeInit()
207 DMA2->INTCLR |= DMA2_CH6_INT_MASK; in DMA_DeInit()
212 DMA2->INTCLR |= DMA2_CH7_INT_MASK; in DMA_DeInit()
219 DMA2->INTCLR |= DMA2_CH8_INT_MASK; in DMA_DeInit()
/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/
A Dn32g45x_dma.c182 DMA2->INTCLR |= DMA2_CH1_INT_MASK; in DMA_DeInit()
187 DMA2->INTCLR |= DMA2_CH2_INT_MASK; in DMA_DeInit()
192 DMA2->INTCLR |= DMA2_CH3_INT_MASK; in DMA_DeInit()
197 DMA2->INTCLR |= DMA2_CH4_INT_MASK; in DMA_DeInit()
202 DMA2->INTCLR |= DMA2_CH5_INT_MASK; in DMA_DeInit()
207 DMA2->INTCLR |= DMA2_CH6_INT_MASK; in DMA_DeInit()
212 DMA2->INTCLR |= DMA2_CH7_INT_MASK; in DMA_DeInit()
219 DMA2->INTCLR |= DMA2_CH8_INT_MASK; in DMA_DeInit()
/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/
A Dn32g45x_dma.c182 DMA2->INTCLR |= DMA2_CH1_INT_MASK; in DMA_DeInit()
187 DMA2->INTCLR |= DMA2_CH2_INT_MASK; in DMA_DeInit()
192 DMA2->INTCLR |= DMA2_CH3_INT_MASK; in DMA_DeInit()
197 DMA2->INTCLR |= DMA2_CH4_INT_MASK; in DMA_DeInit()
202 DMA2->INTCLR |= DMA2_CH5_INT_MASK; in DMA_DeInit()
207 DMA2->INTCLR |= DMA2_CH6_INT_MASK; in DMA_DeInit()
212 DMA2->INTCLR |= DMA2_CH7_INT_MASK; in DMA_DeInit()
219 DMA2->INTCLR |= DMA2_CH8_INT_MASK; in DMA_DeInit()
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/
A Dstm32l1xx_ll_dma.c34 #if defined (DMA1) || defined (DMA2)
76 #if defined (DMA2)
86 (((INSTANCE) == DMA2) && \
103 (((INSTANCE) == DMA2) && \
169 #if defined(DMA2) in LL_DMA_DeInit()
170 else if (DMAx == DMA2) in LL_DMA_DeInit()
/bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/CMSIS/WCH/CH32F20x/Source/ARM/
A Dstartup_ch32f20x.s121 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
122 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
123 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
124 DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
125 DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
147 DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
148 DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
149 DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8
150 DCD DMA2_Channel9_IRQHandler ; DMA2 Channel 9
151 DCD DMA2_Channel10_IRQHandler ; DMA2 Channel 10
[all …]
/bsp/tkm32F499/Libraries/CMSIS_and_startup/
A Dstartup_Tk499.s111 DCD DMA2_Channel1_IRQHandler ;DMA2 Channel 1
112 DCD DMA2_Channel2_IRQHandler ;DMA2 Channel 2
113 DCD DMA2_Channel3_IRQHandler ;DMA2 Channel 3
114 DCD DMA2_Channel4_IRQHandler ;DMA2 Channel 4
115 DCD DMA2_Channel5_IRQHandler ;DMA2 Channel 5
123 DCD DMA2_Channel6_IRQHandler ;DMA2 Channel 6
124 DCD DMA2_Channel7_IRQHandler ;DMA2 Channel 7
125 DCD DMA2_Channel8_IRQHandler ;DMA2 Channel 8
/bsp/apm32/libraries/APM32F4xx_Library/Device/Geehy/APM32F4xx/Source/arm/
A Dstartup_apm32f40x.s130 DCD DMA2_STR0_IRQHandler ; DMA2 Stream 0
131 DCD DMA2_STR1_IRQHandler ; DMA2 Stream 1
132 DCD DMA2_STR2_IRQHandler ; DMA2 Stream 2
133 DCD DMA2_STR3_IRQHandler ; DMA2 Stream 3
134 DCD DMA2_STR4_IRQHandler ; DMA2 Stream 4
142 DCD DMA2_STR5_IRQHandler ; DMA2 Stream 5
143 DCD DMA2_STR6_IRQHandler ; DMA2 Stream 6
144 DCD DMA2_STR7_IRQHandler ; DMA2 Stream 7
A Dstartup_apm32f41x.s130 DCD DMA2_STR0_IRQHandler ; DMA2 Stream 0
131 DCD DMA2_STR1_IRQHandler ; DMA2 Stream 1
132 DCD DMA2_STR2_IRQHandler ; DMA2 Stream 2
133 DCD DMA2_STR3_IRQHandler ; DMA2 Stream 3
134 DCD DMA2_STR4_IRQHandler ; DMA2 Stream 4
142 DCD DMA2_STR5_IRQHandler ; DMA2 Stream 5
143 DCD DMA2_STR6_IRQHandler ; DMA2 Stream 6
144 DCD DMA2_STR7_IRQHandler ; DMA2 Stream 7
/bsp/mm32f327x/Libraries/MM32F327x/Source/IAR_StartAsm/
A Dstartup_mm32f327x_iar.s136 … DCD DMA2_Channel1_IRQHandler ; 56 DMA2 Channel 1
137 … DCD DMA2_Channel2_IRQHandler ; 57 DMA2 Channel 2
138 … DCD DMA2_Channel3_IRQHandler ; 58 DMA2 Channel 3
139 … DCD DMA2_Channel4_IRQHandler ; 59 DMA2 Channel 4
140 … DCD DMA2_Channel5_IRQHandler ; 60 DMA2 Channel 5
/bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Source/Templates/iar/
A Dstartup_mm32f3270.s108 … DCD DMA2_CH1_IRQHandler ; 56 DMA2 Channel 1
109 … DCD DMA2_CH2_IRQHandler ; 57 DMA2 Channel 2
110 … DCD DMA2_CH3_IRQHandler ; 58 DMA2 Channel 3
111 … DCD DMA2_CH4_IRQHandler ; 59 DMA2 Channel 4
112 … DCD DMA2_CH5_IRQHandler ; 60 DMA2 Channel 5
/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/
A Dstartup_apm32f10x_cl.s132 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
133 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
134 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
135 DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
136 DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5

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