| /bsp/mm32f327x/Libraries/MM32F327x/Include/ |
| A D | reg_dma.h | 56 #define DMA2_BASE (AHBPERIPH_BASE + 0x0400) ///< Base Address: … macro
107 #define DMA2 ((DMA_TypeDef*) DMA2_BASE)
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| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/ |
| A D | bl808_memorymap.h | 108 #define DMA2_BASE ((uint32_t)0x30001000) macro
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| /bsp/apm32/libraries/APM32F4xx_Library/Device/Geehy/APM32F4xx/Include/ |
| A D | apm32f4xx.h | 7276 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) macro
7277 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
7278 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
7279 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
7280 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
7281 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
7282 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
7283 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
7284 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
7397 #define DMA2 ((DMA_T *) DMA2_BASE)
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| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/ |
| A D | bl808.h | 452 #define DMA2_BASE ((uint32_t)0x30001000) macro
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| /bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Include/ |
| A D | apm32f0xx.h | 5509 #define DMA2_BASE (AHBPERIPH_BASE + 0x00000400) macro
5510 #define DMA2_CHANNEL_1_BASE (DMA2_BASE + 0x00000008)
5511 #define DMA2_CHANNEL_2_BASE (DMA2_BASE + 0x0000001C)
5512 #define DMA2_CHANNEL_3_BASE (DMA2_BASE + 0x00000030)
5513 #define DMA2_CHANNEL_4_BASE (DMA2_BASE + 0x00000044)
5514 #define DMA2_CHANNEL_5_BASE (DMA2_BASE + 0x00000058)
5575 #define DMA2 ((DMA_T *) DMA2_BASE)
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| /bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/ |
| A D | stm32l100xc.h | 662 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
663 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
664 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
665 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
666 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
667 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
739 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l162xdx.h | 747 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
748 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
749 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
750 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
751 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
752 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
835 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l162xe.h | 747 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
748 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
749 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
750 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
751 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
752 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
835 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l152xc.h | 709 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
710 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
711 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
712 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
713 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
714 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
792 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l152xca.h | 711 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
712 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
713 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
714 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
715 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
716 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
796 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l152xe.h | 726 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
727 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
728 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
729 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
730 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
731 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
813 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l162xc.h | 730 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
731 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
732 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
733 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
734 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
735 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
814 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l162xca.h | 732 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
733 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
734 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
735 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
736 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
737 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
818 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l151xca.h | 695 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
696 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
697 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
698 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
699 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
700 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
779 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l151xdx.h | 710 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
711 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
712 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
713 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
714 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
715 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
796 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l151xe.h | 710 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
711 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
712 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
713 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
714 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
715 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
796 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l151xc.h | 693 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
694 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
695 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
696 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
697 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
698 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
775 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l152xdx.h | 726 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
727 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
728 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
729 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
730 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
731 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
813 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l151xd.h | 756 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
757 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
758 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
759 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
760 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
761 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
851 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l152xd.h | 772 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
773 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
774 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
775 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
776 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
777 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
868 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| A D | stm32l162xd.h | 793 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) macro
794 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
795 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
796 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
797 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
798 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
890 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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| /bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Include/ |
| A D | ch32v10x.h | 568 #define DMA2_BASE (AHBPERIPH_BASE + 0x0400) macro
629 #define DMA2 ((DMA_TypeDef *)DMA2_BASE)
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| /bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ |
| A D | ch32v10x.h | 568 #define DMA2_BASE (AHBPERIPH_BASE + 0x0400) macro
629 #define DMA2 ((DMA_TypeDef *)DMA2_BASE)
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| /bsp/wch/risc-v/Libraries/ch32_drivers/ |
| A D | drv_usart_v2.c | 1324 if ((unsigned int)hdma->Instance < DMA2_BASE) in HAL_DMA_IRQHandler()
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| /bsp/n32/libraries/n32_drivers/ |
| A D | drv_usart_v2.c | 1075 if ((unsigned int)hdma->Instance < DMA2_BASE) in HAL_DMA_IRQHandler()
|