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Searched refs:DMA2_Channel1_BASE (Results 1 – 25 of 28) sorted by relevance

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/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_dma.h57 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) ///< Base Address: … macro
108 #define DMA2_ch1 ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE)
113 #define DMA2_Channel1 ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE)
/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/
A Dhal_dma.c55 if((*(vu32*)&channel) >= (*(vu32*)DMA2_Channel1_BASE)) { in DMA_DeInit()
/bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Include/
A Dch32v10x.h569 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) macro
637 #define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
/bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/
A Dch32v10x.h569 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) macro
637 #define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
/bsp/tkm32F499/Libraries/CMSIS_and_startup/
A Dtk499.h1241 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x6408) macro
1372 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
/bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/CMSIS/WCH/CH32F10x/Include/
A Dch32f10x.h667 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) macro
737 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
/bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/StdPeriph_Driver/inc/
A Dch32f10x.h667 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) macro
737 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
/bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/CMSIS/WCH/CH32F20x/Include/
A Dch32f20x.h1026 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) macro
1128 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
/bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/StdPeriph_Driver/inc/
A Dch32f20x.h1026 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) macro
1128 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
/bsp/apm32/libraries/APM32E10x_Library/Device/Geehy/APM32E10x/Include/
A Dapm32e10x.h5920 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) macro
5987 #define DMA2_Channel1 ((DMA_Channel_T *) DMA2_Channel1_BASE)
/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/
A Dapm32f10x.h6923 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) macro
6994 #define DMA2_Channel1 ((DMA_Channel_T *) DMA2_Channel1_BASE)
/bsp/airm2m/air32f103/libraries/AIR32F10xLib/inc/
A Dair32f10x.h1022 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) macro
1104 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l100xc.h663 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) macro
740 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
A Dstm32l162xdx.h748 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) macro
836 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
A Dstm32l162xe.h748 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) macro
836 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
A Dstm32l152xc.h710 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) macro
793 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
A Dstm32l152xca.h712 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) macro
797 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
A Dstm32l152xe.h727 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) macro
814 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
A Dstm32l162xc.h731 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) macro
815 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
A Dstm32l162xca.h733 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) macro
819 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
A Dstm32l151xca.h696 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) macro
780 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
A Dstm32l151xdx.h711 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) macro
797 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
A Dstm32l151xe.h711 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) macro
797 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
A Dstm32l151xc.h694 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) macro
776 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
A Dstm32l152xdx.h727 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) macro
814 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)

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