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Searched refs:DMA2_Channel5_BASE (Results 1 – 25 of 27) sorted by relevance

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/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_dma.h61 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) ///< Base Address: … macro
112 #define DMA2_ch5 ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE)
117 #define DMA2_Channel5 ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE)
/bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Include/
A Dch32v10x.h573 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) macro
641 #define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
/bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/
A Dch32v10x.h573 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) macro
641 #define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
/bsp/tkm32F499/Libraries/CMSIS_and_startup/
A Dtk499.h1245 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x6458) macro
1376 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
/bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/CMSIS/WCH/CH32F10x/Include/
A Dch32f10x.h671 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) macro
741 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
/bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/StdPeriph_Driver/inc/
A Dch32f10x.h671 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) macro
741 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
/bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/CMSIS/WCH/CH32F20x/Include/
A Dch32f20x.h1030 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) macro
1132 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
/bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/StdPeriph_Driver/inc/
A Dch32f20x.h1030 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) macro
1132 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
/bsp/apm32/libraries/APM32E10x_Library/Device/Geehy/APM32E10x/Include/
A Dapm32e10x.h5924 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) macro
5991 #define DMA2_Channel5 ((DMA_Channel_T *) DMA2_Channel5_BASE)
/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/
A Dapm32f10x.h6927 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) macro
6998 #define DMA2_Channel5 ((DMA_Channel_T *) DMA2_Channel5_BASE)
/bsp/airm2m/air32f103/libraries/AIR32F10xLib/inc/
A Dair32f10x.h1026 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) macro
1108 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l100xc.h667 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) macro
744 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
A Dstm32l162xdx.h752 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) macro
840 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
A Dstm32l162xe.h752 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) macro
840 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
A Dstm32l152xc.h714 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) macro
797 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
A Dstm32l152xca.h716 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) macro
801 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
A Dstm32l152xe.h731 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) macro
818 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
A Dstm32l162xc.h735 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) macro
819 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
A Dstm32l162xca.h737 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) macro
823 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
A Dstm32l151xca.h700 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) macro
784 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
A Dstm32l151xdx.h715 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) macro
801 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
A Dstm32l151xe.h715 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) macro
801 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
A Dstm32l151xc.h698 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) macro
780 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
A Dstm32l152xdx.h731 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) macro
818 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
A Dstm32l151xd.h761 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) macro
856 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)

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