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Searched refs:DMAC (Results 1 – 25 of 119) sorted by relevance

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/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/
A Ddma_crc.h125 DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE; in dma_crc_channel_enable()
136 DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE; in dma_crc_disable()
137 DMAC->CRCCTRL.reg = 0; in dma_crc_disable()
148 DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; in dma_crc_get_checksum()
151 return DMAC->CRCCHKSUM.reg; in dma_crc_get_checksum()
172 if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE) { in dma_crc_io_enable()
181 DMAC->CRCCHKSUM.reg = 0xFFFFFFFF; in dma_crc_io_enable()
184 DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE; in dma_crc_io_enable()
210 DMAC->CRCDATAIN.reg = buffer_8[counter]; in dma_crc_io_calculation()
213 DMAC->CRCDATAIN.reg = buffer_16[counter]; in dma_crc_io_calculation()
[all …]
A Ddma.c174 DMAC->CHCTRLB.reg = temp_CHCTRLB_reg; in _dma_set_config()
205 isr = DMAC->CHINTFLAG.reg; in DMAC_Handler()
215 DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR; in DMAC_Handler()
239 DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP; in DMAC_Handler()
323 DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; in dma_allocate()
324 DMAC->CTRL.reg = DMAC_CTRL_SWRST; in dma_allocate()
352 DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; in dma_allocate()
353 DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST; in dma_allocate()
357 DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; in dma_allocate()
463 DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; in dma_start_transfer_job()
[all …]
/bsp/microchip/samc21/bsp/hpl/dmac/
A Dhpl_dmac.c82 hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); in _dma_init()
83 hri_dmac_clear_CTRL_CRCENABLE_bit(DMAC); in _dma_init()
84 hri_dmac_set_CHCTRLA_SWRST_bit(DMAC); in _dma_init()
86 hri_dmac_write_CTRL_reg(DMAC, in _dma_init()
92 hri_dmac_write_QOSCTRL_reg(DMAC, in _dma_init()
97 DMAC, in _dma_init()
106 hri_dmac_write_CHID_reg(DMAC, i); in _dma_init()
119 hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); in _dma_init()
129 hri_dmac_write_CHID_reg(DMAC, channel); in _dma_set_irq_state()
189 hri_dmac_write_CHID_reg(DMAC, channel); in _dma_enable_transaction()
[all …]
/bsp/microchip/saml10/bsp/hpl/dmac/
A Dhpl_dmac.c82 hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); in _dma_init()
83 hri_dmac_clear_CTRL_CRCENABLE_bit(DMAC); in _dma_init()
84 hri_dmac_set_CHCTRLA_SWRST_bit(DMAC); in _dma_init()
86 hri_dmac_write_CTRL_reg(DMAC, in _dma_init()
93 DMAC, in _dma_init()
102 hri_dmac_write_CHID_reg(DMAC, i); in _dma_init()
117 hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); in _dma_init()
127 hri_dmac_write_CHID_reg(DMAC, channel); in _dma_set_irq_state()
187 hri_dmac_write_CHID_reg(DMAC, channel); in _dma_enable_transaction()
189 hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC); in _dma_enable_transaction()
[all …]
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hpl/dmac/
A Dhpl_dmac.c85 hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); in _dma_init()
87 hri_dmac_set_CTRL_SWRST_bit(DMAC); in _dma_init()
88 while (hri_dmac_get_CTRL_SWRST_bit(DMAC)) in _dma_init()
91 hri_dmac_write_CTRL_reg(DMAC, in _dma_init()
98 DMAC, in _dma_init()
120 hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); in _dma_init()
189 hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC, channel); in _dma_enable_transaction()
192 hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); in _dma_enable_transaction()
219 if (hri_dmac_get_INTPEND_TERR_bit(DMAC)) { in _dmac_handler()
220 hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel); in _dmac_handler()
[all …]
/bsp/microchip/same54/bsp/hpl/dmac/
A Dhpl_dmac.c85 hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); in _dma_init()
87 hri_dmac_set_CTRL_SWRST_bit(DMAC); in _dma_init()
88 while (hri_dmac_get_CTRL_SWRST_bit(DMAC)) in _dma_init()
91 hri_dmac_write_CTRL_reg(DMAC, in _dma_init()
98 DMAC, in _dma_init()
120 hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); in _dma_init()
189 hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC, channel); in _dma_enable_transaction()
192 hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); in _dma_enable_transaction()
219 if (hri_dmac_get_INTPEND_TERR_bit(DMAC)) { in _dmac_handler()
220 hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel); in _dmac_handler()
[all …]
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hpl/dmac/
A Dhpl_dmac.c85 hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); in _dma_init()
87 hri_dmac_set_CTRL_SWRST_bit(DMAC); in _dma_init()
88 while (hri_dmac_get_CTRL_SWRST_bit(DMAC)) in _dma_init()
91 hri_dmac_write_CTRL_reg(DMAC, in _dma_init()
98 DMAC, in _dma_init()
120 hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); in _dma_init()
189 hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC, channel); in _dma_enable_transaction()
192 hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); in _dma_enable_transaction()
219 if (hri_dmac_get_INTPEND_TERR_bit(DMAC)) { in _dmac_handler()
220 hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel); in _dmac_handler()
[all …]
/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/
A Dstart_rvds.S97 DCD DMAC0_Handler ; 38: DMAC ch.0
98 DCD DMAC1_Handler ; 39: DMAC ch.1
99 DCD DMAC2_Handler ; 40: DMAC ch.2
100 DCD DMAC3_Handler ; 41: DMAC ch.3
101 DCD DMAC4_Handler ; 42: DMAC ch.4
102 DCD DMAC5_Handler ; 43: DMAC ch.5
103 DCD DMAC6_Handler ; 44: DMAC ch.6
104 DCD DMAC7_Handler ; 45: DMAC ch.7
A Dstart_iar.S113 DCD DMAC0_IRQHandler ; DMAC ch.0
114 DCD DMAC1_IRQHandler ; DMAC ch.1
115 DCD DMAC2_IRQHandler ; DMAC ch.2
116 DCD DMAC3_IRQHandler ; DMAC ch.3
117 DCD DMAC4_IRQHandler ; DMAC ch.4
118 DCD DMAC5_IRQHandler ; DMAC ch.5
119 DCD DMAC6_IRQHandler ; DMAC ch.6
120 DCD DMAC7_IRQHandler ; DMAC ch.7
/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/ARM/
A Dstartup_mb9bf50x.S126 DCD DMAC0_Handler ; 38: DMAC ch.0
127 DCD DMAC1_Handler ; 39: DMAC ch.1
128 DCD DMAC2_Handler ; 40: DMAC ch.2
129 DCD DMAC3_Handler ; 41: DMAC ch.3
130 DCD DMAC4_Handler ; 42: DMAC ch.4
131 DCD DMAC5_Handler ; 43: DMAC ch.5
132 DCD DMAC6_Handler ; 44: DMAC ch.6
133 DCD DMAC7_Handler ; 45: DMAC ch.7
/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/arm/
A Dstartup_mb9bf61x.S126 DCD DMAC0_Handler ; 38: DMAC ch.0
127 DCD DMAC1_Handler ; 39: DMAC ch.1
128 DCD DMAC2_Handler ; 40: DMAC ch.2
129 DCD DMAC3_Handler ; 41: DMAC ch.3
130 DCD DMAC4_Handler ; 42: DMAC ch.4
131 DCD DMAC5_Handler ; 43: DMAC ch.5
132 DCD DMAC6_Handler ; 44: DMAC ch.6
133 DCD DMAC7_Handler ; 45: DMAC ch.7
/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/IAR/
A Dstartup_mb9bf50x.S107 DCD DMAC0_Handler ; 38: DMAC ch.0
108 DCD DMAC1_Handler ; 39: DMAC ch.1
109 DCD DMAC2_Handler ; 40: DMAC ch.2
110 DCD DMAC3_Handler ; 41: DMAC ch.3
111 DCD DMAC4_Handler ; 42: DMAC ch.4
112 DCD DMAC5_Handler ; 43: DMAC ch.5
113 DCD DMAC6_Handler ; 44: DMAC ch.6
114 DCD DMAC7_Handler ; 45: DMAC ch.7
/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/iar/
A Dstartup_mb9bf61x.S107 DCD DMAC0_Handler ; 38: DMAC ch.0
108 DCD DMAC1_Handler ; 39: DMAC ch.1
109 DCD DMAC2_Handler ; 40: DMAC ch.2
110 DCD DMAC3_Handler ; 41: DMAC ch.3
111 DCD DMAC4_Handler ; 42: DMAC ch.4
112 DCD DMAC5_Handler ; 43: DMAC ch.5
113 DCD DMAC6_Handler ; 44: DMAC ch.6
114 DCD DMAC7_Handler ; 45: DMAC ch.7
/bsp/renesas/rzn2l_etherkit/
A Drzn_cfg.txt28 Master MPU: MPU0 : DMAC Unit0: Region 0 Start: 0x00000000
29 Master MPU: MPU0 : DMAC Unit0: Region 0 End: 0x00000C00
32 Master MPU: MPU0 : DMAC Unit0: Region 1 Start: 0x00000000
33 Master MPU: MPU0 : DMAC Unit0: Region 1 End: 0x00000C00
37 Master MPU: MPU0 : DMAC Unit0: Region 2 End: 0x00000C00
41 Master MPU: MPU0 : DMAC Unit0: Region 3 End: 0x00000C00
45 Master MPU: MPU0 : DMAC Unit0: Region 4 End: 0x00000C00
49 Master MPU: MPU0 : DMAC Unit0: Region 5 End: 0x00000C00
53 Master MPU: MPU0 : DMAC Unit0: Region 6 End: 0x00000C00
57 Master MPU: MPU0 : DMAC Unit0: Region 7 End: 0x00000C00
[all …]
/bsp/renesas/rzn2l_rsk/
A Drzn_cfg.txt28 Master MPU: MPU0 : DMAC Unit0: Region 0 Start: 0x00000000
29 Master MPU: MPU0 : DMAC Unit0: Region 0 End: 0x00000C00
32 Master MPU: MPU0 : DMAC Unit0: Region 1 Start: 0x00000000
33 Master MPU: MPU0 : DMAC Unit0: Region 1 End: 0x00000C00
37 Master MPU: MPU0 : DMAC Unit0: Region 2 End: 0x00000C00
41 Master MPU: MPU0 : DMAC Unit0: Region 3 End: 0x00000C00
45 Master MPU: MPU0 : DMAC Unit0: Region 4 End: 0x00000C00
49 Master MPU: MPU0 : DMAC Unit0: Region 5 End: 0x00000C00
53 Master MPU: MPU0 : DMAC Unit0: Region 6 End: 0x00000C00
57 Master MPU: MPU0 : DMAC Unit0: Region 7 End: 0x00000C00
[all …]
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/iar/
A Dstartup_samd21.c242 DMAC->QOSCTRL.bit.DQOS = 2; in Reset_Handler()
243 DMAC->QOSCTRL.bit.FQOS = 2; in Reset_Handler()
244 DMAC->QOSCTRL.bit.WRBQOS = 2; in Reset_Handler()
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/gcc/
A Dstartup_samd21.c258 DMAC->QOSCTRL.bit.DQOS = 2; in Reset_Handler()
259 DMAC->QOSCTRL.bit.FQOS = 2; in Reset_Handler()
260 DMAC->QOSCTRL.bit.WRBQOS = 2; in Reset_Handler()
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/
A Dsamd21e15a.h366 #define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
415 #define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
417 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
A Dsamd21e15l.h358 #define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
407 #define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
409 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
A Dsamd21e16a.h366 #define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
415 #define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
417 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
A Dsamd21e16l.h358 #define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
407 #define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
409 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
A Dsamd21e17a.h366 #define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
415 #define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
417 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
A Dsamd21e18a.h366 #define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
415 #define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
417 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
A Dsamd21g17a.h374 #define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
425 #define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
427 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
A Dsamd21g17au.h382 #define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
435 #define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ macro
437 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */

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