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Searched refs:DMAR (Results 1 – 25 of 50) sorted by relevance

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/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/
A Dstm32l1xx_hal_tim.c4255 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4273 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4291 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4309 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4327 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4345 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4545 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)Bur… in HAL_TIM_DMABurst_MultiReadStart()
4563 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
4581 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
4599 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
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/bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/
A Dhal_tim_16b.c281 return (uint32_t)(&(TIMx->DMAR)); in TIM_16B_EnableDMABurst()
A Dhal_tim_32b.c281 return (uint32_t)(&(TIMx->DMAR)); in TIM_32B_EnableDMABurst()
A Dhal_tim_adv.c322 return (uint32_t)(&(TIMx->DMAR)); in TIM_ADV_EnableDMABurst()
/bsp/fm33lc026/libraries/FM/FM33xx/Include/
A Dfm33lc0xx.h177 …__IO uint32_t DMAR; /*!< ATIM DMA Access Register, Address … member
325 …__IO uint32_t DMAR; /*!< GPTIM DMA access Register, Address … member
A Dfm33lg0xx.h637 …__IO uint32_t DMAR; /*!< ATIM DMA Access Register, … member
668 …__IO uint32_t DMAR; /*!< GPTIMx DMA access Register, … member
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/
A Dfm33lc0xx.h177 …__IO uint32_t DMAR; /*!< ATIM DMA Access Register, Address … member
325 …__IO uint32_t DMAR; /*!< GPTIM DMA access Register, Address … member
A Dfm33lg0xx.h637 …__IO uint32_t DMAR; /*!< ATIM DMA Access Register, … member
668 …__IO uint32_t DMAR; /*!< GPTIMx DMA access Register, … member
/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_tim.h88 …__IO u32 DMAR; ///< TIM DMA address f… member
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/
A Dfm33lc0xx_fl_gptim.h1997 MODIFY_REG(TIMx->DMAR, (0xffffU << 0U), (address << 0U)); in FL_GPTIM_WriteDMAAddress()
2008 return (uint32_t)(READ_BIT(TIMx->DMAR, 0xffffU) >> 0U); in FL_GPTIM_ReadDMAAddress()
A Dfm33lc0xx_fl_atim.h2484 MODIFY_REG(TIMx->DMAR, (0xffffU << 0U), (address << 0U)); in FL_ATIM_WriteDMAAddress()
2495 return (uint32_t)(READ_BIT(TIMx->DMAR, 0xffffU) >> 0U); in FL_ATIM_ReadDMAAddress()
/bsp/acm32/acm32f0x0-nucleo/libraries/Device/
A DACM32F0x0.h160 __IO uint32_t DMAR; // 0x4C member
/bsp/acm32/acm32f4xx-nucleo/libraries/Device/
A DACM32F4.h191 __IO uint32_t DMAR; member
/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/
A Dft32f030x6.h587 …__IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0… member
A Dft32f030x8.h618 …__IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0… member
A Dft32f072x8.h633 …__IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0… member
A Dft32f032x8.h627 …__IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0… member
A Dft32f032x6.h627 …__IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0… member
A Dft32f072xb.h681 …__IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0… member
/bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Include/
A Dmm32f3277g.h2715 …__IO uint32_t DMAR; ///< DMA address in … member
3464 …__IO uint32_t DMAR; ///< DMA address in … member
4008 …__IO uint32_t DMAR; ///< DMA address in … member
/bsp/mm32l3xx/Libraries/MM32L3xx/Include/
A DMM32L3xx.h731 __IO uint16_t DMAR; member
/bsp/mm32f103x/Libraries/MM32F103/Include/
A DMM32F103.h740 __IO uint16_t DMAR; member
/bsp/tkm32F499/Libraries/CMSIS_and_startup/
A Dtk499.h793 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ member
/bsp/mm32l07x/Libraries/MM32L0xx/Include/
A DMM32L0xx.h657 __IO uint32_t DMAR; member
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f030x4x6x8.h415 …__IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0… member

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