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Searched refs:DMA_BASE (Results 1 – 25 of 103) sorted by relevance

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/bsp/raspberry-pi/raspi4-32/driver/
A Ddrv_dma.h18 #define DMA_BASE (DMA_PER_BASE+0x7000) macro
19 #define DMA_INT_STATUS (DMA_BASE + 0xFE0) //Interrupt Status of each DMA Channel
20 #define DMA_ENABLE (DMA_BASE + 0xFF0) //Global Enable bits for each DMA Channel */
27 #define DMA_CS(dch) __REG32(DMA_BASE + dch*0x100 + 0x000) /* Control and Status …
28 #define DMA_CONBLK_AD(dch) __REG32(DMA_BASE + dch*0x100 + 0x004) /* Control Block Addre…
30 #define DMA_SOURCE_AD(dch) __REG32(DMA_BASE + dch*0x100 + 0x00c) /* CB Word 1(Source Ad…
31 #define DMA_DEST_AD(dch) __REG32(DMA_BASE + dch*0x100 + 0x010) /* CB Word 2(Destinati…
32 #define DMA_TXFR_LEN(dch) __REG32(DMA_BASE + dch*0x100 + 0x014) /* CB Word 3(Transfer …
33 #define DMA_STRIDE(dch) __REG32(DMA_BASE + dch*0x100 + 0x018) /* CB Word 4(2D Stride…
34 #define DMA_NEXTCONBK(dch) __REG32(DMA_BASE + dch*0x100 + 0x01c) /* CB Word 5(Next CB A…
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl602/
A Ddevice_table.c61 .reg_base = DMA_BASE + 1 * DMA_CHANNEL_OFFSET,
68 .reg_base = DMA_BASE + 2 * DMA_CHANNEL_OFFSET,
75 .reg_base = DMA_BASE + 3 * DMA_CHANNEL_OFFSET,
82 .reg_base = DMA_BASE + 4 * DMA_CHANNEL_OFFSET,
89 .reg_base = DMA_BASE + 5 * DMA_CHANNEL_OFFSET,
96 .reg_base = DMA_BASE + 6 * DMA_CHANNEL_OFFSET,
103 .reg_base = DMA_BASE + 7 * DMA_CHANNEL_OFFSET,
110 .reg_base = DMA_BASE + 8 * DMA_CHANNEL_OFFSET,
A Dbl602_memorymap.h60 #define DMA_BASE ((uint32_t)0x4000C000) macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl702/
A Ddevice_table.c61 .reg_base = DMA_BASE + 1 * DMA_CHANNEL_OFFSET,
68 .reg_base = DMA_BASE + 2 * DMA_CHANNEL_OFFSET,
75 .reg_base = DMA_BASE + 3 * DMA_CHANNEL_OFFSET,
82 .reg_base = DMA_BASE + 4 * DMA_CHANNEL_OFFSET,
89 .reg_base = DMA_BASE + 5 * DMA_CHANNEL_OFFSET,
96 .reg_base = DMA_BASE + 6 * DMA_CHANNEL_OFFSET,
103 .reg_base = DMA_BASE + 7 * DMA_CHANNEL_OFFSET,
110 .reg_base = DMA_BASE + 8 * DMA_CHANNEL_OFFSET,
A Dbl702_memorymap.h79 #define DMA_BASE ((uint32_t)0x4000C000) macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/
A Ddevice_table.c62 .reg_base = DMA_BASE + 1 * DMA_CHANNEL_OFFSET,
69 .reg_base = DMA_BASE + 2 * DMA_CHANNEL_OFFSET,
76 .reg_base = DMA_BASE + 3 * DMA_CHANNEL_OFFSET,
83 .reg_base = DMA_BASE + 4 * DMA_CHANNEL_OFFSET,
90 .reg_base = DMA_BASE + 5 * DMA_CHANNEL_OFFSET,
97 .reg_base = DMA_BASE + 6 * DMA_CHANNEL_OFFSET,
104 .reg_base = DMA_BASE + 7 * DMA_CHANNEL_OFFSET,
111 .reg_base = DMA_BASE + 8 * DMA_CHANNEL_OFFSET,
A Dbl616_memorymap.h88 #define DMA_BASE ((uint32_t)0x2000c000) macro
/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/
A Des32vf2264.h117 #define DMA_BASE (AHB_BASE + 0x5400) macro
175 #define DMA ((DMA_TypeDef *) DMA_BASE)
/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Include/
A Defm32g880f128.h279 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ macro
321 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
A Defm32g880f32.h279 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ macro
321 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
A Defm32g880f64.h279 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ macro
321 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
A Defm32g890f128.h279 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ macro
321 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
A Defm32g890f32.h279 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ macro
321 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
A Defm32g890f64.h279 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ macro
321 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
/bsp/Vango/v85xx/Libraries/CMSIS/Vango/V85xx/Include/
A Dtarget.h544 #define DMA_BASE (APBPERIPH_BASE + 0x00000000) macro
596 #define DMA ((DMA_TypeDef *) DMA_BASE)
4619 #define DMA_IE (volatile unsigned *)(DMA_BASE + 0x0000)
4620 #define DMA_STS (volatile unsigned *)(DMA_BASE + 0x0004)
4621 #define DMA_C0CTL (volatile unsigned *)(DMA_BASE + 0x0010)
4622 #define DMA_C0SRC (volatile unsigned *)(DMA_BASE + 0x0014)
4623 #define DMA_C0DST (volatile unsigned *)(DMA_BASE + 0x0018)
4624 #define DMA_C0LEN (volatile unsigned *)(DMA_BASE + 0x001C)
4625 #define DMA_C1CTL (volatile unsigned *)(DMA_BASE + 0x0020)
4626 #define DMA_C1SRC (volatile unsigned *)(DMA_BASE + 0x0024)
[all …]
/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Include/
A Defm32gg990f512.h324 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ macro
373 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
A Defm32gg995f1024.h324 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ macro
373 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
A Defm32gg995f512.h324 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ macro
373 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
A Defm32gg980f1024.h324 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ macro
373 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
A Defm32gg980f512.h324 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ macro
373 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
A Defm32gg990f1024.h324 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ macro
373 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
/bsp/airm2m/air105/libraries/HAL_Driver/Inc/
A Dair105.h977 #define DMA_BASE (AIR105_AHB_BASE + 0x0800) macro
1066 #define DMA ((DMA_MODULE_TypeDef *)DMA_BASE)
1067 #define DMA_Channel_0 ((DMA_TypeDef *)DMA_BASE)
1068 #define DMA_Channel_1 ((DMA_TypeDef *)(DMA_BASE + 0x58))
1069 #define DMA_Channel_2 ((DMA_TypeDef *)(DMA_BASE + 0x58*2))
1070 #define DMA_Channel_3 ((DMA_TypeDef *)(DMA_BASE + 0x58*3))
1071 #define DMA_Channel_4 ((DMA_TypeDef *)(DMA_BASE + 0x58*4))
1072 #define DMA_Channel_5 ((DMA_TypeDef *)(DMA_BASE + 0x58*5))
1073 #define DMA_Channel_6 ((DMA_TypeDef *)(DMA_BASE + 0x58*6))
1074 #define DMA_Channel_7 ((DMA_TypeDef *)(DMA_BASE + 0x58*7))
/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/
A Dgd32vf103_dma.h43 #define DMA0 (DMA_BASE) /*!< DMA0 base address */
44 #define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */
/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/
A Dgd32vf103.h225 #define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address … macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/
A Dbl602.h171 #define DMA_BASE ((uint32_t)0x4000C000) macro

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