Home
last modified time | relevance | path

Searched refs:DMA_IFCR_CGIF1_Pos (Results 1 – 25 of 26) sorted by relevance

12

/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_dma.h184 #define DMA_IFCR_CGIF1_Pos (0) macro
185 #define DMA_IFCR_CGIF1 (0x01U << DMA_IFCR_CGIF1_Pos) ///< Channel 1 Glob…
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f030x4x6x8.h1072 #define DMA_IFCR_CGIF1_Pos (0U) macro
1073 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dhk32f031x4x6.h1050 #define DMA_IFCR_CGIF1_Pos (0U) macro
1051 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dhk32f04ax4x6x8.h1118 #define DMA_IFCR_CGIF1_Pos (0U) macro
1119 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l100xb.h1904 #define DMA_IFCR_CGIF1_Pos (0U) macro
1905 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l100xba.h1907 #define DMA_IFCR_CGIF1_Pos (0U) macro
1908 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l151xb.h1905 #define DMA_IFCR_CGIF1_Pos (0U) macro
1906 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l151xba.h1908 #define DMA_IFCR_CGIF1_Pos (0U) macro
1909 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l152xb.h1922 #define DMA_IFCR_CGIF1_Pos (0U) macro
1923 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l152xba.h1910 #define DMA_IFCR_CGIF1_Pos (0U) macro
1911 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l100xc.h1980 #define DMA_IFCR_CGIF1_Pos (0U) macro
1981 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l162xdx.h2332 #define DMA_IFCR_CGIF1_Pos (0U) macro
2333 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l162xe.h2332 #define DMA_IFCR_CGIF1_Pos (0U) macro
2333 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l152xc.h2142 #define DMA_IFCR_CGIF1_Pos (0U) macro
2143 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l152xca.h2185 #define DMA_IFCR_CGIF1_Pos (0U) macro
2186 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l152xe.h2202 #define DMA_IFCR_CGIF1_Pos (0U) macro
2203 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l162xc.h2272 #define DMA_IFCR_CGIF1_Pos (0U) macro
2273 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l162xca.h2315 #define DMA_IFCR_CGIF1_Pos (0U) macro
2316 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l151xca.h2168 #define DMA_IFCR_CGIF1_Pos (0U) macro
2169 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l151xdx.h2185 #define DMA_IFCR_CGIF1_Pos (0U) macro
2186 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l151xe.h2185 #define DMA_IFCR_CGIF1_Pos (0U) macro
2186 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l151xc.h2125 #define DMA_IFCR_CGIF1_Pos (0U) macro
2126 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l152xdx.h2202 #define DMA_IFCR_CGIF1_Pos (0U) macro
2203 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l151xd.h2284 #define DMA_IFCR_CGIF1_Pos (0U) macro
2285 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
A Dstm32l152xd.h2301 #define DMA_IFCR_CGIF1_Pos (0U) macro
2302 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */

Completed in 1608 milliseconds

12