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Searched refs:DMA_IFCR_CHTIF5_Pos (Results 1 – 25 of 26) sorted by relevance

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/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_dma.h220 #define DMA_IFCR_CHTIF5_Pos (18) macro
221 #define DMA_IFCR_CHTIF5 (0x01U << DMA_IFCR_CHTIF5_Pos) ///< Channel 5 Half…
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f030x4x6x8.h1126 #define DMA_IFCR_CHTIF5_Pos (18U) macro
1127 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dhk32f031x4x6.h1104 #define DMA_IFCR_CHTIF5_Pos (18U) macro
1105 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dhk32f04ax4x6x8.h1172 #define DMA_IFCR_CHTIF5_Pos (18U) macro
1173 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l100xb.h1958 #define DMA_IFCR_CHTIF5_Pos (18U) macro
1959 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l100xba.h1961 #define DMA_IFCR_CHTIF5_Pos (18U) macro
1962 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l151xb.h1959 #define DMA_IFCR_CHTIF5_Pos (18U) macro
1960 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l151xba.h1962 #define DMA_IFCR_CHTIF5_Pos (18U) macro
1963 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l152xb.h1976 #define DMA_IFCR_CHTIF5_Pos (18U) macro
1977 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l152xba.h1964 #define DMA_IFCR_CHTIF5_Pos (18U) macro
1965 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l100xc.h2034 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2035 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l162xdx.h2386 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2387 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l162xe.h2386 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2387 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l152xc.h2196 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2197 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l152xca.h2239 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2240 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l152xe.h2256 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2257 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l162xc.h2326 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2327 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l162xca.h2369 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2370 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l151xca.h2222 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2223 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l151xdx.h2239 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2240 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l151xe.h2239 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2240 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l151xc.h2179 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2180 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l152xdx.h2256 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2257 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l151xd.h2338 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2339 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
A Dstm32l152xd.h2355 #define DMA_IFCR_CHTIF5_Pos (18U) macro
2356 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */

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