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Searched refs:DMA_IFCR_CTCIF2_Pos (Results 1 – 25 of 26) sorted by relevance

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/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_dma.h194 #define DMA_IFCR_CTCIF2_Pos (5) macro
195 #define DMA_IFCR_CTCIF2 (0x01U << DMA_IFCR_CTCIF2_Pos) ///< Channel 2 Tran…
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f030x4x6x8.h1087 #define DMA_IFCR_CTCIF2_Pos (5U) macro
1088 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dhk32f031x4x6.h1065 #define DMA_IFCR_CTCIF2_Pos (5U) macro
1066 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dhk32f04ax4x6x8.h1133 #define DMA_IFCR_CTCIF2_Pos (5U) macro
1134 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l100xb.h1919 #define DMA_IFCR_CTCIF2_Pos (5U) macro
1920 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l100xba.h1922 #define DMA_IFCR_CTCIF2_Pos (5U) macro
1923 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l151xb.h1920 #define DMA_IFCR_CTCIF2_Pos (5U) macro
1921 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l151xba.h1923 #define DMA_IFCR_CTCIF2_Pos (5U) macro
1924 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l152xb.h1937 #define DMA_IFCR_CTCIF2_Pos (5U) macro
1938 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l152xba.h1925 #define DMA_IFCR_CTCIF2_Pos (5U) macro
1926 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l100xc.h1995 #define DMA_IFCR_CTCIF2_Pos (5U) macro
1996 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l162xdx.h2347 #define DMA_IFCR_CTCIF2_Pos (5U) macro
2348 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l162xe.h2347 #define DMA_IFCR_CTCIF2_Pos (5U) macro
2348 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l152xc.h2157 #define DMA_IFCR_CTCIF2_Pos (5U) macro
2158 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l152xca.h2200 #define DMA_IFCR_CTCIF2_Pos (5U) macro
2201 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l152xe.h2217 #define DMA_IFCR_CTCIF2_Pos (5U) macro
2218 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l162xc.h2287 #define DMA_IFCR_CTCIF2_Pos (5U) macro
2288 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l162xca.h2330 #define DMA_IFCR_CTCIF2_Pos (5U) macro
2331 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l151xca.h2183 #define DMA_IFCR_CTCIF2_Pos (5U) macro
2184 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l151xdx.h2200 #define DMA_IFCR_CTCIF2_Pos (5U) macro
2201 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l151xe.h2200 #define DMA_IFCR_CTCIF2_Pos (5U) macro
2201 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l151xc.h2140 #define DMA_IFCR_CTCIF2_Pos (5U) macro
2141 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l152xdx.h2217 #define DMA_IFCR_CTCIF2_Pos (5U) macro
2218 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l151xd.h2299 #define DMA_IFCR_CTCIF2_Pos (5U) macro
2300 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
A Dstm32l152xd.h2316 #define DMA_IFCR_CTCIF2_Pos (5U) macro
2317 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */

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