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Searched refs:DMA_IFCR_CTCIF3_Pos (Results 1 – 25 of 26) sorted by relevance

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/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_dma.h202 #define DMA_IFCR_CTCIF3_Pos (9) macro
203 #define DMA_IFCR_CTCIF3 (0x01U << DMA_IFCR_CTCIF3_Pos) ///< Channel 3 Tran…
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f030x4x6x8.h1099 #define DMA_IFCR_CTCIF3_Pos (9U) macro
1100 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dhk32f031x4x6.h1077 #define DMA_IFCR_CTCIF3_Pos (9U) macro
1078 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dhk32f04ax4x6x8.h1145 #define DMA_IFCR_CTCIF3_Pos (9U) macro
1146 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l100xb.h1931 #define DMA_IFCR_CTCIF3_Pos (9U) macro
1932 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l100xba.h1934 #define DMA_IFCR_CTCIF3_Pos (9U) macro
1935 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l151xb.h1932 #define DMA_IFCR_CTCIF3_Pos (9U) macro
1933 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l151xba.h1935 #define DMA_IFCR_CTCIF3_Pos (9U) macro
1936 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l152xb.h1949 #define DMA_IFCR_CTCIF3_Pos (9U) macro
1950 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l152xba.h1937 #define DMA_IFCR_CTCIF3_Pos (9U) macro
1938 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l100xc.h2007 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2008 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l162xdx.h2359 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2360 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l162xe.h2359 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2360 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l152xc.h2169 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2170 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l152xca.h2212 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2213 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l152xe.h2229 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2230 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l162xc.h2299 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2300 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l162xca.h2342 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2343 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l151xca.h2195 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2196 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l151xdx.h2212 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2213 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l151xe.h2212 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2213 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l151xc.h2152 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2153 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l152xdx.h2229 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2230 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l151xd.h2311 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2312 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
A Dstm32l152xd.h2328 #define DMA_IFCR_CTCIF3_Pos (9U) macro
2329 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */

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