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Searched refs:DMA_ISR_HTIF5_Pos (Results 1 – 25 of 26) sorted by relevance

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/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_dma.h159 #define DMA_ISR_HTIF5_Pos (18) macro
160 #define DMA_ISR_HTIF5 (0x01U << DMA_ISR_HTIF5_Pos) ///< Channel 5 Half…
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f030x4x6x8.h1064 #define DMA_ISR_HTIF5_Pos (18U) macro
1065 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dhk32f031x4x6.h1042 #define DMA_ISR_HTIF5_Pos (18U) macro
1043 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dhk32f04ax4x6x8.h1110 #define DMA_ISR_HTIF5_Pos (18U) macro
1111 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l100xb.h1872 #define DMA_ISR_HTIF5_Pos (18U) macro
1873 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l100xba.h1875 #define DMA_ISR_HTIF5_Pos (18U) macro
1876 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l151xb.h1873 #define DMA_ISR_HTIF5_Pos (18U) macro
1874 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l151xba.h1876 #define DMA_ISR_HTIF5_Pos (18U) macro
1877 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l152xb.h1890 #define DMA_ISR_HTIF5_Pos (18U) macro
1891 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l152xba.h1878 #define DMA_ISR_HTIF5_Pos (18U) macro
1879 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l100xc.h1948 #define DMA_ISR_HTIF5_Pos (18U) macro
1949 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l162xdx.h2300 #define DMA_ISR_HTIF5_Pos (18U) macro
2301 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l162xe.h2300 #define DMA_ISR_HTIF5_Pos (18U) macro
2301 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l152xc.h2110 #define DMA_ISR_HTIF5_Pos (18U) macro
2111 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l152xca.h2153 #define DMA_ISR_HTIF5_Pos (18U) macro
2154 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l152xe.h2170 #define DMA_ISR_HTIF5_Pos (18U) macro
2171 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l162xc.h2240 #define DMA_ISR_HTIF5_Pos (18U) macro
2241 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l162xca.h2283 #define DMA_ISR_HTIF5_Pos (18U) macro
2284 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l151xca.h2136 #define DMA_ISR_HTIF5_Pos (18U) macro
2137 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l151xdx.h2153 #define DMA_ISR_HTIF5_Pos (18U) macro
2154 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l151xe.h2153 #define DMA_ISR_HTIF5_Pos (18U) macro
2154 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l151xc.h2093 #define DMA_ISR_HTIF5_Pos (18U) macro
2094 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l152xdx.h2170 #define DMA_ISR_HTIF5_Pos (18U) macro
2171 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l151xd.h2252 #define DMA_ISR_HTIF5_Pos (18U) macro
2253 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
A Dstm32l152xd.h2269 #define DMA_ISR_HTIF5_Pos (18U) macro
2270 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */

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