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Searched refs:DMA_ISR_TCIF1_Pos (Results 1 – 25 of 26) sorted by relevance

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/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_dma.h125 #define DMA_ISR_TCIF1_Pos (1) macro
126 #define DMA_ISR_TCIF1 (0x01U << DMA_ISR_TCIF1_Pos) ///< Channel 1 Tran…
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f030x4x6x8.h1013 #define DMA_ISR_TCIF1_Pos (1U) macro
1014 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dhk32f031x4x6.h991 #define DMA_ISR_TCIF1_Pos (1U) macro
992 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dhk32f04ax4x6x8.h1059 #define DMA_ISR_TCIF1_Pos (1U) macro
1060 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l100xb.h1821 #define DMA_ISR_TCIF1_Pos (1U) macro
1822 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l100xba.h1824 #define DMA_ISR_TCIF1_Pos (1U) macro
1825 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l151xb.h1822 #define DMA_ISR_TCIF1_Pos (1U) macro
1823 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l151xba.h1825 #define DMA_ISR_TCIF1_Pos (1U) macro
1826 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l152xb.h1839 #define DMA_ISR_TCIF1_Pos (1U) macro
1840 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l152xba.h1827 #define DMA_ISR_TCIF1_Pos (1U) macro
1828 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l100xc.h1897 #define DMA_ISR_TCIF1_Pos (1U) macro
1898 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l162xdx.h2249 #define DMA_ISR_TCIF1_Pos (1U) macro
2250 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l162xe.h2249 #define DMA_ISR_TCIF1_Pos (1U) macro
2250 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l152xc.h2059 #define DMA_ISR_TCIF1_Pos (1U) macro
2060 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l152xca.h2102 #define DMA_ISR_TCIF1_Pos (1U) macro
2103 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l152xe.h2119 #define DMA_ISR_TCIF1_Pos (1U) macro
2120 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l162xc.h2189 #define DMA_ISR_TCIF1_Pos (1U) macro
2190 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l162xca.h2232 #define DMA_ISR_TCIF1_Pos (1U) macro
2233 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l151xca.h2085 #define DMA_ISR_TCIF1_Pos (1U) macro
2086 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l151xdx.h2102 #define DMA_ISR_TCIF1_Pos (1U) macro
2103 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l151xe.h2102 #define DMA_ISR_TCIF1_Pos (1U) macro
2103 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l151xc.h2042 #define DMA_ISR_TCIF1_Pos (1U) macro
2043 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l152xdx.h2119 #define DMA_ISR_TCIF1_Pos (1U) macro
2120 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l151xd.h2201 #define DMA_ISR_TCIF1_Pos (1U) macro
2202 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
A Dstm32l152xd.h2218 #define DMA_ISR_TCIF1_Pos (1U) macro
2219 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */

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