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Searched refs:DMA_ISR_TCIF2_Pos (Results 1 – 25 of 26) sorted by relevance

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/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_dma.h133 #define DMA_ISR_TCIF2_Pos (5) macro
134 #define DMA_ISR_TCIF2 (0x01U << DMA_ISR_TCIF2_Pos) ///< Channel 2 Tran…
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f030x4x6x8.h1025 #define DMA_ISR_TCIF2_Pos (5U) macro
1026 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dhk32f031x4x6.h1003 #define DMA_ISR_TCIF2_Pos (5U) macro
1004 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dhk32f04ax4x6x8.h1071 #define DMA_ISR_TCIF2_Pos (5U) macro
1072 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l100xb.h1833 #define DMA_ISR_TCIF2_Pos (5U) macro
1834 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l100xba.h1836 #define DMA_ISR_TCIF2_Pos (5U) macro
1837 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l151xb.h1834 #define DMA_ISR_TCIF2_Pos (5U) macro
1835 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l151xba.h1837 #define DMA_ISR_TCIF2_Pos (5U) macro
1838 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l152xb.h1851 #define DMA_ISR_TCIF2_Pos (5U) macro
1852 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l152xba.h1839 #define DMA_ISR_TCIF2_Pos (5U) macro
1840 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l100xc.h1909 #define DMA_ISR_TCIF2_Pos (5U) macro
1910 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l162xdx.h2261 #define DMA_ISR_TCIF2_Pos (5U) macro
2262 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l162xe.h2261 #define DMA_ISR_TCIF2_Pos (5U) macro
2262 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l152xc.h2071 #define DMA_ISR_TCIF2_Pos (5U) macro
2072 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l152xca.h2114 #define DMA_ISR_TCIF2_Pos (5U) macro
2115 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l152xe.h2131 #define DMA_ISR_TCIF2_Pos (5U) macro
2132 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l162xc.h2201 #define DMA_ISR_TCIF2_Pos (5U) macro
2202 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l162xca.h2244 #define DMA_ISR_TCIF2_Pos (5U) macro
2245 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l151xca.h2097 #define DMA_ISR_TCIF2_Pos (5U) macro
2098 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l151xdx.h2114 #define DMA_ISR_TCIF2_Pos (5U) macro
2115 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l151xe.h2114 #define DMA_ISR_TCIF2_Pos (5U) macro
2115 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l151xc.h2054 #define DMA_ISR_TCIF2_Pos (5U) macro
2055 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l152xdx.h2131 #define DMA_ISR_TCIF2_Pos (5U) macro
2132 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l151xd.h2213 #define DMA_ISR_TCIF2_Pos (5U) macro
2214 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
A Dstm32l152xd.h2230 #define DMA_ISR_TCIF2_Pos (5U) macro
2231 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */

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