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Searched refs:DMA_ISR_TCIF5_Pos (Results 1 – 25 of 26) sorted by relevance

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/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_dma.h157 #define DMA_ISR_TCIF5_Pos (17) macro
158 #define DMA_ISR_TCIF5 (0x01U << DMA_ISR_TCIF5_Pos) ///< Channel 5 Tran…
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f030x4x6x8.h1061 #define DMA_ISR_TCIF5_Pos (17U) macro
1062 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dhk32f031x4x6.h1039 #define DMA_ISR_TCIF5_Pos (17U) macro
1040 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dhk32f04ax4x6x8.h1107 #define DMA_ISR_TCIF5_Pos (17U) macro
1108 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l100xb.h1869 #define DMA_ISR_TCIF5_Pos (17U) macro
1870 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l100xba.h1872 #define DMA_ISR_TCIF5_Pos (17U) macro
1873 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l151xb.h1870 #define DMA_ISR_TCIF5_Pos (17U) macro
1871 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l151xba.h1873 #define DMA_ISR_TCIF5_Pos (17U) macro
1874 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l152xb.h1887 #define DMA_ISR_TCIF5_Pos (17U) macro
1888 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l152xba.h1875 #define DMA_ISR_TCIF5_Pos (17U) macro
1876 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l100xc.h1945 #define DMA_ISR_TCIF5_Pos (17U) macro
1946 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l162xdx.h2297 #define DMA_ISR_TCIF5_Pos (17U) macro
2298 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l162xe.h2297 #define DMA_ISR_TCIF5_Pos (17U) macro
2298 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l152xc.h2107 #define DMA_ISR_TCIF5_Pos (17U) macro
2108 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l152xca.h2150 #define DMA_ISR_TCIF5_Pos (17U) macro
2151 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l152xe.h2167 #define DMA_ISR_TCIF5_Pos (17U) macro
2168 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l162xc.h2237 #define DMA_ISR_TCIF5_Pos (17U) macro
2238 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l162xca.h2280 #define DMA_ISR_TCIF5_Pos (17U) macro
2281 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l151xca.h2133 #define DMA_ISR_TCIF5_Pos (17U) macro
2134 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l151xdx.h2150 #define DMA_ISR_TCIF5_Pos (17U) macro
2151 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l151xe.h2150 #define DMA_ISR_TCIF5_Pos (17U) macro
2151 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l151xc.h2090 #define DMA_ISR_TCIF5_Pos (17U) macro
2091 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l152xdx.h2167 #define DMA_ISR_TCIF5_Pos (17U) macro
2168 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l151xd.h2249 #define DMA_ISR_TCIF5_Pos (17U) macro
2250 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
A Dstm32l152xd.h2266 #define DMA_ISR_TCIF5_Pos (17U) macro
2267 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */

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